US4951114A
Expired / Lapsed
US
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Complementary metal electrode semiconductor device
Assignee: Raytheon Co
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Filing: 1988-12-05
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Granted: 1990-08-21
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Expires: 2008-12-05
Abstract
Abstract A semiconductor device referred to as complementary metal electrode semiconductor (CMES) has p-type and n-type silicon MESFETs interconnected on a substrate with an n-type barrier enhancement implanted into the p-channel of the p-type MESFET. The structure and method of fabrication are provided for forming a CMES logic inverter which has characteristics of very low power, low voltage, low noise and high speed.
Inventors
- 👤 Edward T. Lewis
- 👤 Dale L. Montrone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:46
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/86
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
87 words
A semiconductor device comprising: an enhancement mode n-channel field effect transistor having a metal electrode for coupling to a first control signal; an enhancement mode p-channel field effect transistor having a metal electrode for coupling to a second control signal; an n-type barrier enhancement implanted into a shallow portion of the p-channel of said p-channel enhancement mode field effect transistor for providing an enhanced forward Schottky voltage; and means for serially coupling said enhancement mode n-channel field effect transistor to said enhancement mode p-channel field effect transistor.
Claim 2
Dependent Claim
87 words
A semiconductor device comprising: an enhancement mode n-channel field effect transistor having a metal electrode for coupling to a first control signal; an enhancement mode p-channel field effect transistor having a metal electrode for coupling to a second control signal; an n-type barrier enhancement implanted into a shallow portion of the p-channel of said p-channel enhancement mode field effect transistor for providing an enhanced forward Schottky voltage; and means for serially coupling said enhancement mode n-channel field effect transistor to said enhancement mode p-channel field effect transistor.
Claim 3
Dependent Claim
33 words
The semiconductor device as recited in claim 1 wherein: said device comprises contact means for interconnecting said first control signal and said second control signal to form a complementary metal electrode semiconductor device.
Claim 4
Dependent Claim
31 words
The semiconductor device as recited in claim 1 wherein: said serially coupling means connects a drain of said p-channel field effect transistor to a drain of said n-channel field effect transistor.
Claim 5
Dependent Claim
104 words
A CMES inverter logic device comprising: a twin well MESFET structure on a silicon substrate having a p-channel field effect transistor in an n-well and an n-channel field effect transistor in a p-well; an n-type barrier enhancement implanted into a shallow portion of the p-channel of said p-channel field effect transistor for providing an enhanced forward Schottky voltage; means for coupling a drain of said p-channel field effect transistor to a drain of said n-channel field effect transistor; and contact means for coupling a metal electrode gate of said p-channel field effect transistor to a metal electrode gate of said n-channel field effect transistor.
Claim 6
Dependent Claim
104 words
A CMES inverter logic device comprising: a twin well MESFET structure on a silicon substrate having a p-channel field effect transistor in an n-well and an n-channel field effect transistor in a p-well; an n-type barrier enhancement implanted into a shallow portion of the p-channel of said p-channel field effect transistor for providing an enhanced forward Schottky voltage; means for coupling a drain of said p-channel field effect transistor to a drain of said n-channel field effect transistor; and contact means for coupling a metal electrode gate of said p-channel field effect transistor to a metal electrode gate of said n-channel field effect transistor.
References Cited (Backward Citations)
JPS58148451A
Cited
JPS6276680A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |