Memory cell made by selective oxidation of polysilicon

Claim 1

A semiconductor dynamic memory device arranged to be connected in an array of dynamic memory devices between one work address line and one bit line, said device comprising: a silicon body having a P minus epitaxial layer grown on said body; a gate lying within a gate region, connected to said one word address line for the array, said gate being formed at least by applying a gate oxide layer on said epitaxial layer and forming a conductive layer including a silicide material over the gate oxide for connection to said one word address line; a channel formed in said epitaxial layer below said gate by using a mask over the gate region to mask a portion of said epitaxial layer against doping; a source and a drain formed on opposite sides of said gate and said channel in said epitaxial layer, said source and drain being parts of respective source and drain regions that are formed, at least in part, by using the mask over the gate region to place N plus dopant into said epitaxial layer on both sides of said gate and channel, said drain being of substantially even thickness; a storage capacitor including a PN junction spaced laterally from said channel and formed by a second masking step diffusing a P plus dopant into a portion of the epitaxial layer and below part of what will be one of the source and drain regions; and a connection between the other of the source and drain regions to said one bit line.