US4329704A
Expired / Lapsed
US
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MOS Random access memory with buried storage capacitor
Assignee: Fujitsu Ltd
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Filing: 1979-09-19
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Granted: 1982-05-11
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Expires: 1999-09-19
Abstract
Abstract A one transistor, one capacitance type dynamic MOS.RAM is provided with a buried storage capacitor and a planar transfer electrode. The MOS.RAM is, therefore, characterized by a small size of the memory cells and a simple production process. One process feature of the present invention is that a quick diffusion through polycrystalline silicon is employed for forming a vertical connection between the buried storage capacitor and the source or drain of the MOS transistor.
Inventors
- 👤 Junji Sakurai
- 👤 Kiyoshi Miyasaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10B12/33; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40; H10W20/00; H10W20/01; H10W20/021
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
212 words
A semiconductor memory device comprising an array of memory cells, each said memory cell comprising: a substrate of a semiconductor material having a first conductivity type; a semiconductor growth layer on said substrate including a single crystalline region of the same conductivity type as said substrate and polycrystalline region, said single crystalline region comprising a first layer having a relatively high impurity concentration formed on said substrate and a second layer having a relatively low impurity concentration formed on said first layer; a buried semiconductor layer of the opposite conductivity type between a selected portion of the area between said substrate and said single crystalline region of said semiconductor growth layer; a buried insulating layer adjacent to said buried semiconductor layer, said polycrystalline region of said semiconductor growth layer being formed over said buried insulating layer; a first single crystalline impurity region of said opposite conductivity type formed in a selected portion of said single crystalline region of said growth layer; a second single crystalline impurity region of said opposite conductivity type extending from the top surface of said semiconductor growth layer to said buried semiconductor layer and being adjacent to said polycrystalline region, and a planar transfer electrode formed over a region separating said first and second single crystalline impurity regions.
Claim 2
Dependent Claim
212 words
A semiconductor memory device comprising an array of memory cells, each said memory cell comprising: a substrate of a semiconductor material having a first conductivity type; a semiconductor growth layer on said substrate including a single crystalline region of the same conductivity type as said substrate and polycrystalline region, said single crystalline region comprising a first layer having a relatively high impurity concentration formed on said substrate and a second layer having a relatively low impurity concentration formed on said first layer; a buried semiconductor layer of the opposite conductivity type between a selected portion of the area between said substrate and said single crystalline region of said semiconductor growth layer; a buried insulating layer adjacent to said buried semiconductor layer, said polycrystalline region of said semiconductor growth layer being formed over said buried insulating layer; a first single crystalline impurity region of said opposite conductivity type formed in a selected portion of said single crystalline region of said growth layer; a second single crystalline impurity region of said opposite conductivity type extending from the top surface of said semiconductor growth layer to said buried semiconductor layer and being adjacent to said polycrystalline region, and a planar transfer electrode formed over a region separating said first and second single crystalline impurity regions.
Claim 3
Dependent Claim
38 words
A semiconductor memory device according to claim 1, wherein said second single crystalline impurity region comprises a shallow portion on the surface of the semiconductor growth layer and a vertical connecting portion extending to said buried semiconductor layer.
Claim 4
Dependent Claim
60 words
A semiconductor memory device according to claim 1, wherein said first layer of said single crystalline region of said semiconductor growth layer has an impurity concentration in the range of from 5×10 16 to 5×10 18 /cm 3 , and said second layer has an impurity concentration in the range of from 5×10 13 to 5×10 15 /cm 3 .
Claim 5
Dependent Claim
68 words
The device of claim 3, said high impurity concentration of said first layer of said single crystalline region of said semiconductor growth layer being in the range from 5×10 17 to 1×10 18 /cm 3 , and said low impurity concentration of said second layer of said single crystalline region of said semiconductor growth layer being in the range from 1×10 14 to 1×10 15 /cm 3 .
Claim 6
Dependent Claim
51 words
The device of claim 1, 2 or 3, said first layer of said single crystalline region of said semiconductor growth layer having a thickness from 2000 to 3000 angstroms, and said second layer of said single crystalline region of said semiconductor growth layer having a thickness from 5000 to 10,000 angstroms.
Claim 7
Dependent Claim
31 words
The device of claim 1 or 2, said low impurity concentration being so low that said second layer of said single crystalline region of said semiconductor growth layer is essentially undoped.
Claim 8
Dependent Claim
99 words
The device of claim 1, 2, 3 or 4, each said buried insulating layer of each said memory cell of said array surrounding the respective memory cell and having an oxide portion extending to the surface of said semiconductor growth layer, each said cell comprising two of said buried semiconductor layers, two of said second single crystalline impurity regions respectively connected to said two buried semiconductor layers, one of said first single crystalline impurity regions, and two of said planar transfer electrodes respectively separating said one first single crystalline impurity region from said two second single crystalline impurity regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |