One transistor dynamic memory cell

Claim 1

A dynamic data storage cell comprising: a. a semiconductor substrate of one conductivity type; b. a first elongated diffused region of opposite conductivity type extending to the surface of said substrate; c. a second diffused region of said opposite conductivity spaced from said first diffused region and substantially parallel thereto, said second diffused region also extending to the surface of said substrate; d. a third diffused region underlying said second diffused region, of said one conductivity type and having a lower resistivity than said substrate, formed within at least a portion of the area occupied by said second diffused region, forming a P-N junction therewith; e. an insulating layer covering the surface of said substrate, said insulating layer having a first thin region overlying an area of said substrate bridging said first and second diffused regions thereby defining a channel of a FET, and a second thin region overlying a portion of said second diffused region; f. a first elongated conductive region extending over said first thin insulating region, thereby forming a gate of said FET, said conductive region substantially orthogonal to said first diffused region; g. a second elongated conductive region spaced from and substantially parallel to said first elongated conductive region, extending over said second thin region to form a capacitor; and h. means for connecting said second conductive region to said substrate.