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JPH05109986A Expired / Lapsed JP ⏱️ 0.0 years remaining

Method for manufacturing semiconductor device

Assignee: Seiko Epson Corp
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Filing: 1991-10-18
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Granted: —
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Expires: 2011-10-18
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Abstract

Abstract Translated from Japanese (57)【要約】 【目的】 多結晶シリコン層からなる抵抗素子を具備す る半導体装置の製造方法において、熱処理を行わない で、多結晶シリコン層からなる抵抗素子以外の半導体素 子の特性に悪影響を与えずに、多結晶シリコン中の結晶 粒のサイズを大きくすることにより、熱処理による抵抗 値が低下が抑えられ、しかも、抵抗値の温度依存性の小 さい多結晶シリコン層からなる抵抗素子を具備する半導 体装置の製造方法を提供するところにある。 【構成】 半導体基板1上に多結晶シリコン層3を形成 する工程と、該多結晶シリコン層3の表面から一定量の 多結晶シリコンを除去する工程を具備することを特徴と する半導体装置の製造方法。 (57) [Summary] [Object] In a method of manufacturing a semiconductor device including a resistance element formed of a polycrystalline silicon layer, heat treatment is not performed, and characteristics of semiconductor elements other than the resistance element formed of the polycrystalline silicon layer are adversely affected. By increasing the size of the crystal grains in the polycrystalline silicon without giving it, the resistance value is suppressed from being lowered by the heat treatment, and a resistance element composed of a polycrystalline silicon layer having a small temperature dependence of the resistance value is provided. A method of manufacturing a semiconductor device is provided. A semiconductor device comprising: a step of forming a polycrystalline silicon layer 3 on a semiconductor substrate 1; and a step of removing a certain amount of polycrystalline silicon from the surface of the polycrystalline silicon layer 3. Method.

Inventors

  • 👤 Kunio Watanabe
  • 👤 邦雄 渡辺

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 14:34
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