US5767004A
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Method for forming a low impurity diffusion polysilicon layer
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1996-04-22
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Granted: 1998-06-16
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Expires: 2016-04-22
Abstract
Abstract A method for forming within an integrated circuit a low impurity diffusion polysilicon layer. Formed upon a semiconductor substrate is an amorphous silicon layer. Formed also upon the semiconductor substrate and contacting the amorphous silicon layer is a polysilicon layer. The amorphous silicon layer and the polysilicon layer are then simultaneously annealed to form a low impurity diffusion polysilicon layer. The low impurity diffusion polysilicon layer is a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties. Optionally, a metal silicide layer may be formed upon the amorphous silicon layer and the polysilicon layer either prior to or subsequent to annealing the amorphous silicon layer and the polysilicon layer. The metal silicide layer and low impurity diffusion polysilicon layer may then be patterned to form a polycide gate electrode.
Inventors
- 👤 Narayanan Balasubramanian
- 👤 Ching Win Kong
- 👤 Chuck Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 13:52
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10P; H10P14/00; H10P14/40; H10P14/416
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
123 words
A method for forming an impurity diffusion inhibited polysilicon layer comprising: forming over a semiconductor substrate an amorphous silicon layer; forming over the semiconductor substrate a polysilicon layer in contact with the amorphous silicon layer; annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties; and forming adjoining the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer.
Claim 2
Independent Claim
123 words
A method for forming an impurity diffusion inhibited polysilicon layer comprising: forming over a semiconductor substrate an amorphous silicon layer; forming over the semiconductor substrate a polysilicon layer in contact with the amorphous silicon layer; annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer with grain boundary mis-matched polycrystalline properties; and forming adjoining the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer.
Claim 3
Dependent Claim
19 words
The method of claim 1 wherein the amorphous silicon layer is from about 400 to about 700 angstroms thick.
Claim 4
Dependent Claim
28 words
The method of claim 1 wherein the amorphous silicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silicon source material.
Claim 5
Dependent Claim
29 words
The method of claim 3 wherein the Low Pressure Chemical Vapor Deposition (LPVCD) method is undertaken at a deposition temperature of from about 500 to about 580 degrees centigrade.
Claim 6
Dependent Claim
18 words
The method of claim 1 wherein the polysilicon layer is from about 1000 to about 1500 angstroms thick.
Claim 7
Dependent Claim
27 words
The method of claim 1 wherein the polysilicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silicon source material.
Claim 8
Dependent Claim
29 words
The method of claim 6 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 600 to about 700 degrees centigrade.
Claim 9
Dependent Claim
47 words
The method of claim 1 wherein the amorphous silicon layer and the polysilicon layer are simultaneously thermally annealed through a conventional thermal method at a temperature of from about 800 to about 950 degrees centigrade for a time period of from about 15 to about 45 minutes.
Claim 10
Dependent Claim
26 words
The method of claim 1 wherein the amorphous silicon layer is formed over the semiconductor substrate prior to forming the polysilicon layer over the semiconductor substrate.
Claim 11
Dependent Claim
26 words
The method of claim 1 wherein the polysilicon layer is formed over the semiconductor substrate prior to forming the amorphous silicon layer over the semiconductor substrate.
Claim 12
Independent Claim
151 words
A method for forming an impurity diffusion inhibited polycide gate electrode for use within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising: forming over a semiconductor substrate an amorphous silicon layer; forming over the semiconductor substrate a polysilicon layer contacting the amorphous silicon layer; annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer having grain boundary mis-matched polycrystalline properties; forming contacting the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer; and patterning the metal silicide layer and the impurity diffusion inhibited polysilicon layer to form a polycide gate electrode.
Claim 13
Independent Claim
151 words
A method for forming an impurity diffusion inhibited polycide gate electrode for use within a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising: forming over a semiconductor substrate an amorphous silicon layer; forming over the semiconductor substrate a polysilicon layer contacting the amorphous silicon layer; annealing simultaneously the amorphous silicon layer and the polysilicon layer to form an impurity diffusion inhibited polysilicon layer, the impurity diffusion inhibited polysilicon layer being a polysilicon multi-layer having grain boundary mis-matched polycrystalline properties; forming contacting the impurity diffusion inhibited polysilicon layer a metal silicide layer, the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities from within the impurity diffusion inhibited polysilicon layer and the impurity diffusion inhibited polysilicon layer inhibiting diffusion of impurities through the impurity diffusion inhibited polysilicon layer from the metal silicide layer; and patterning the metal silicide layer and the impurity diffusion inhibited polysilicon layer to form a polycide gate electrode.
Claim 14
Dependent Claim
19 words
The method of claim 11 wherein the amorphous silicon layer is from about 400 to about 700 angstroms thick.
Claim 15
Dependent Claim
28 words
The method of claim 11 wherein the amorphous silicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silane source material.
Claim 16
Dependent Claim
29 words
The method of claim 13 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 500 to about 580 degrees centigrade.
Claim 17
Dependent Claim
18 words
The method of claim 11 wherein the polysilicon layer is from about 1000 to about 1500 angstroms thick.
Claim 18
Dependent Claim
27 words
The method of claim 11 wherein the polysilicon layer is formed through a Low Pressure Chemical Vapor Deposition (LPCVD) method employing silicone as a silane source material.
Claim 19
Dependent Claim
29 words
The method of claim 16 wherein the Low Pressure Chemical Vapor Deposition (LPCVD) method is undertaken at a deposition temperature of from about 600 to about 700 degrees centigrade.
Claim 20
Dependent Claim
46 words
The method of claim 11 wherein the amorphous silicon layer and the polysilicon layer are thermally annealed through a conventional thermal method at a temperature of from about 800 to about 950 degrees centigrade for a time period of from about 15 to about 45 minutes.
Claim 21
Dependent Claim
26 words
The method of claim 11 wherein the amorphous silicon layer is formed over the semiconductor substrate prior to forming the polysilicon layer over the semiconductor substrate.
Claim 22
Dependent Claim
15 words
The method of claim 11 wherein the metal silicide layer is a tungsten silicide layer.
Claim 23
Dependent Claim
26 words
The method of claim 20 wherein the tungsten silicide is formed through a Chemical Vapor Deposition (CVD) method employing tungsten hexafluoride as a tungsten source material.
Claim 24
Dependent Claim
32 words
The method of claim 1 wherein the metal silicide layer the is a tungsten silicide layer formed through a Chemical Vapor Deposition (CVD) method employing tungsten hexafluoride as a tungsten source material.
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