Patent DE2506524C3 successfully refreshed from Google Patents.
Patent US6580124B1 successfully refreshed from Google Patents.
US6580124B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multigate semiconductor device with vertical channel current and method of fabrication
Assignee: SanDisk Technologies LLC
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Filing: 2000-08-14
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Granted: 2003-06-17
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Expires: 2020-08-14
Abstract
Abstract The present invention is a multibit nonvolatile memory and its method of fabrication. According to the present invention a silicon channel body having a first and second channel surface is formed. A charge storage medium is formed adjacent to the first channel surface and a second charge storage medium is formed adjacent to the second channel surface. A first control gate is formed adjacent to the first charge storage medium adjacent to the first channel surface and a second control gate is formed adjacent to the second charge storage medium adjacent to the second surface.
Inventors
- 👤 James M. Cleeves
- 👤 Vivek Subramanian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:50
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/0413; H10D30/60; H10D30/68; H10D30/681; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10D64/037; G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5671; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; G11C16/0466; G11C16/0475; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5611; G11C2211/5612
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
182 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region; a second source/drain region of the first conductivity type formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium comprising nanocrystals formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; and a fourth control gate adjacent to said charge storage medium adjacent to said fourth face.
Claim 2
Dependent Claim
182 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region; a second source/drain region of the first conductivity type formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium comprising nanocrystals formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; and a fourth control gate adjacent to said charge storage medium adjacent to said fourth face.
Claim 3
Dependent Claim
193 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region; a second source/drain region of the first conductivity type formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; and a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein said charge storage medium is an oxide with H+ ions therein.
Claim 4
Dependent Claim
193 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type formed on the first source/drain region; a second source/drain region of the first conductivity type formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; and a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein said charge storage medium is an oxide with H+ ions therein.
Claim 5
Dependent Claim
26 words
The memory of claim 1 wherein the channel region of said first face and the channel region of said third face have a different doping density.
Claim 6
Dependent Claim
186 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region; a channel region formed on the first source/drain region; second source/drain region formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein the channel region of said first face and the channel region of said third face have a different doping density; and the charge storage medium comprises nanocrystals.
Claim 7
Dependent Claim
186 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region; a channel region formed on the first source/drain region; second source/drain region formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein the channel region of said first face and the channel region of said third face have a different doping density; and the charge storage medium comprises nanocrystals.
Claim 8
Dependent Claim
41 words
The memory of claim 4 wherein the channel region of said first face, the channel region of said second face, the channel region of said third face, and the channel region of said fourth face each have a different doping density.
Claim 9
Dependent Claim
156 words
A multibit nonvolatile memory comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region, a second source/drain region of the first conductivity type on said channel region; a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface, wherein the first, the second and the third charge storage medium comprise nanocrystals; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and a third control gate adjacent to said third charge storage medium adjacent to said third channel surface.
Claim 10
Dependent Claim
156 words
A multibit nonvolatile memory comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region, a second source/drain region of the first conductivity type on said channel region; a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface, wherein the first, the second and the third charge storage medium comprise nanocrystals; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and a third control gate adjacent to said third charge storage medium adjacent to said third channel surface.
Claim 11
Dependent Claim
160 words
A multibit nonvolatile memory comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region, a second source/drain region of the first conductivity type on said channel region; a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and a third control gate adjacent to said third charge storage medium adjacent to said third channel surface; and wherein said first, second and third charge storage medium is an oxide with H+ ions therein.
Claim 12
Dependent Claim
160 words
A multibit nonvolatile memory comprising: a first source/drain region of a first conductivity type; a channel region of a second conductivity type different from the first conductivity type having a first, a second and a third channel surface formed on said first source/drain region, a second source/drain region of the first conductivity type on said channel region; a first charge storage medium adjacent to said first channel surface, a second charge storage medium adjacent to said second channel surface, and a third charge storage medium adjacent to said third channel surface; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; a second control gate adjacent to said second charge storage medium adjacent to said second channel surface; and a third control gate adjacent to said third charge storage medium adjacent to said third channel surface; and wherein said first, second and third charge storage medium is an oxide with H+ ions therein.
Claim 13
Dependent Claim
35 words
The memory of claim 6 wherein a first portion of the channel region adjacent to said first surface and a second portion of the channel region adjacent to second surface have a different doping density.
Claim 14
Dependent Claim
33 words
The memory of claim 6 further comprising a fourth charge storage medium adjacent to a fourth surface of said channel region and a fourth control gate adjacent to said fourth charge storage medium.
Claim 15
Dependent Claim
61 words
The memory of claim 9 wherein a first portion of the channel region adjacent to said first surface, a second portion of the channel region adjacent to said second surface, a third portion of the channel region adjacent to said third surface, and a fourth portion of the channel region adjacent to said fourth surface each have a different doping density.
Claim 16
Dependent Claim
18 words
The memory of claim 6 wherein said first, said second and said third control gates are independently controllable.
Claim 17
Dependent Claim
192 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region; a channel region formed on the first source/drain region; a second source/drain region formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein the channel region of said first face and the channel region of said third face have a different doping density; and said charge storage medium comprises an oxide with H+ ions therein.
Claim 18
Dependent Claim
192 words
A multibit nonvolatile pillar memory comprising: a pillar comprising: a first source/drain region; a channel region formed on the first source/drain region; a second source/drain region formed on the channel region; wherein said first source/drain region, said channel region, and said second source/drain region are in alignment and wherein said pillar has a first face and a second face opposite said first face, a third face adjacent to said first face and a fourth face opposite said third face; a charge storage medium formed adjacent to each of said first, second, third and forth face of said pillar; a first control gate adjacent to said charge storage medium adjacent to said first face; a second control gate adjacent to said charge storage medium adjacent to said second face; a third control gate adjacent to said charge storage medium adjacent to said third face; a fourth control gate adjacent to said charge storage medium adjacent to said fourth face; and wherein the channel region of said first face and the channel region of said third face have a different doping density; and said charge storage medium comprises an oxide with H+ ions therein.
Claim 19
Dependent Claim
140 words
A multibit nonvolatile memory comprising: a first source/drain region; a channel region having a first and a second channel surface formed on said first source/drain region, wherein a first portion of the channel region adjacent to said first surface, and a second portion of the channel region adjacent to second surface have a different doping density; a second source/drain region on said channel region; a first charge storage medium adjacent to said first channel surface and a second charge storage medium adjacent to said second channel surface, wherein the first and the second charge storage medium comprise nanocrystals or an oxide with H+ ions therein; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; and a second control gate adjacent to said second charge storage medium adjacent to said second channel surface.
Claim 20
Dependent Claim
140 words
A multibit nonvolatile memory comprising: a first source/drain region; a channel region having a first and a second channel surface formed on said first source/drain region, wherein a first portion of the channel region adjacent to said first surface, and a second portion of the channel region adjacent to second surface have a different doping density; a second source/drain region on said channel region; a first charge storage medium adjacent to said first channel surface and a second charge storage medium adjacent to said second channel surface, wherein the first and the second charge storage medium comprise nanocrystals or an oxide with H+ ions therein; a first control gate adjacent to said first charge storage medium adjacent to said first channel surface; and a second control gate adjacent to said second charge storage medium adjacent to said second channel surface.
Claim 21
Dependent Claim
60 words
The memory of claim 13 further comprising: a third charge storage medium adjacent to a third surface of said channel region and a third control gate adjacent to said third charge storage medium; and a fourth charge storage medium adjacent to a fourth surface of said channel region and a fourth control gate adjacent to said fourth charge storage medium.
Claim 22
Dependent Claim
23 words
The memory of claim 14 wherein the third and the fourth charge storage medium comprise nanocrystals or an oxide with H+ ions therein.
Claim 23
Dependent Claim
61 words
The memory of claim 14 wherein the first portion of the channel region adjacent to said first surface, the second portion of the channel region adjacent to said second surface, a third portion of the channel region adjacent to said third surface, and a fourth portion of the channel region adjacent to said fourth surface each have a different doping density.
Claim 24
Dependent Claim
16 words
The memory of claim 13 wherein said first and said second control gates are independently controllable.
Claim 25
Dependent Claim
19 words
The memory of claim 13 wherein the first charge storage medium and the second charge storage medium comprise nanocrystals.
Claim 26
Dependent Claim
24 words
The memory of claim 13 wherein the first charge storage medium and the second charge storage medium comprise an oxide with H+ ions therein.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-16 | 2006-12-16 | 2007-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-16 | 2010-12-16 | 2011-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-16 | 2014-12-16 | 2015-06-17 | $7700.00 | Window Closed / Lapsed |