US3922648A
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US
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Method and means for preventing degradation of threshold voltage of filament-forming memory semiconductor device
Assignee: Energy Conversion Devices Inc
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Filing: 1974-08-19
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Granted: 1975-11-25
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Expires: 1994-08-19
Abstract
Abstract The number of set and reset cycles to which a filament-type amorphous memory switch device can be operated without threshold degradation is found unexpectedly to be a function of reset current pulse width, the number of reset current pulses used to effect each resetting operation and the spacing of the reset current pulses. In one case, for low current reset, it was determined each reset operation should comprise a burst of at least about 10 and preferably about 50-150 reset current pulses to effect homogenization of the reset filament, each reset current pulse should be substantially under 10 microseconds in width, and the pulse spacing should be substantially less than the threshold recovery period of the memory switch device, preferably much less than 10 microseconds. Such a burst of a large number of reset current pulses are particularly useful in setting memory switch devices in very low current rated circuits. In such case, the initial low amplitude reset current pulses fully reset the filament path and the following low amplitude reset current pulses homogenize the filament path.
Inventors
- 👤 William D Buckley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:49
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/0002; G11C13/0009; G11C13/0011; G11C13/0004; G11C13/0021; G11C13/0069; H; H03; H03K; H03K17/00; H03K3/00; H03K3/02; G11C2013/0092; G11C2213/00; G11C2213/70; G11C2213/72
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
223 words
A method of resetting a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrodes has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination thereof the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition, said memory semiconductor material being such that immediately after each reset current pulse flows through the previously set filamentous path the threshold voltage value thereof drops to a minimum temporary threshold voltage value and gradually rises to a stabilized threshold voltage value over a recovery period, said method comprising: applying to said electrodes a burst of reset voltage pulses spaced apart a fractional part of said recovery period and each of a value in excess of the temporary threshold voltage value, so reset current pulses are produced thereby each of which at least partially converts the crystalline filamentous path into a substantially amorphous condition.
Claim 2
Independent Claim
223 words
A method of resetting a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrodes has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination thereof the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition, said memory semiconductor material being such that immediately after each reset current pulse flows through the previously set filamentous path the threshold voltage value thereof drops to a minimum temporary threshold voltage value and gradually rises to a stabilized threshold voltage value over a recovery period, said method comprising: applying to said electrodes a burst of reset voltage pulses spaced apart a fractional part of said recovery period and each of a value in excess of the temporary threshold voltage value, so reset current pulses are produced thereby each of which at least partially converts the crystalline filamentous path into a substantially amorphous condition.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein the spacing between said pulses is much less than 10 microseconds.
Claim 4
Dependent Claim
20 words
The method of claim 2 wherein each of said reset current pulses has a width substantially less than 10 microseconds.
Claim 5
Dependent Claim
27 words
The method of claim 3 wherein there is at least about 10 pulses in each burst of reset current pulses and substantially less than about 150 pulses.
Claim 6
Dependent Claim
57 words
The method of claim 1 wherein the number of said reset voltage pulses and reset current pulses produced thereby are substantially in excess of the number needed to reset all of the resettable portions of the filamentous path to its maximum resistance condition to homogenize the same and prevent crystallization from developing therein under elevated temperature conditions.
Claim 7
Dependent Claim
20 words
The method of claim 1 wherein the spacing between the reset current pulse is no greater than about 6 MICROSECONDS.
Claim 8
Dependent Claim
77 words
The method of claim 1 wherein said memory semiconductor material has the general formula: GeATeBXCYD where: A 5 to 60 atomic percent B 30 to 95 atomic percent C 0 to 10 atomic percent when X is Antimony (Sb) or Bismuth (Bi) or C 0 to 40 atomic percent when X is Arsenic (As) D 0 to 10 atomic percent when Y is Sulphur (S) or D 0 to 20 atomic percent when Y is Selenium (Se).
Claim 9
Dependent Claim
27 words
The method of claim 5 wherein each reset current pulse is so low it only resets a small fraction of the filamentous path to an amorphous condition.
Claim 10
Dependent Claim
57 words
The method of claim 8 wherein the number of said reset voltage pulses and reset current pulses produced thereby are substantially in excess of the number needed to reset all of the resettable portions of the filamentous path to its maximum resistance condition to homogenize the same and prevent crystallization from developing therein under elevated temperature conditions.
Claim 11
Dependent Claim
24 words
The method of claim 7 wherein each of said reset current pulses in each burst of reset current pulses is substantially under 50 milliamps.
Claim 12
Dependent Claim
86 words
The method of claim 7 wherein the amplitude of each of said reset current pulses in each burst of reset current pulses is a fraction substantially less than one-half the amplitude required substantially to fully reset the entire crystalline filament, the number of pulses in each burst of pulses being at least about 10, the spacing between said pulses is no greater than about 6 microseconds and the duration of each of said reset current pulses is a small fraction of the spacing between successive pulses.
Claim 13
Independent Claim
160 words
A method of resetting a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrodes has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination thereof the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition, said method comprising: applying to said electrodes a burst of reset voltage pulses which are so very closely spaced that the temperature of the filament being reset cools only partially to ambient temperature in the interval between successive reset current pulses.
Claim 14
Independent Claim
160 words
A method of resetting a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrodes has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination thereof the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition, said method comprising: applying to said electrodes a burst of reset voltage pulses which are so very closely spaced that the temperature of the filament being reset cools only partially to ambient temperature in the interval between successive reset current pulses.
Claim 15
Dependent Claim
206 words
In combination, a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrode has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament of a given amplitude which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition; and a source of reset voltage for resetting said path to its initial amorphous condition, said source being selectively connectable to said electrodes for applying thereto for each reset operation a burst of reset voltage pulses spaced apart a fractional part of said recovery period and each of a value in excess of the tempoRary threshold voltage value, so reset current pulses are produced thereby each of which at least partially converts the crystalline filamentous path into a substantially amorphous condition.
Claim 16
Dependent Claim
206 words
In combination, a filament-type memory device including spaced electrodes between which extend a body of generally amorphous non-conductive memory semiconductor material which, when a set voltage pulse in excess of a threshold voltage value and duration is applied to said electrode has formed therein a crystalline low resistance filament resettable into a generally amorphous condition by application of one or more reset voltage pulses producing reset current pulses through said filament of a given amplitude which heat the same to a temperature which dissipates substantially the entire crystalline filament and are of a duration which is so short that upon termination of each reset current pulse the filament will be quickly quenched to leave at least portions of the filament in a substantially amorphous condition; and a source of reset voltage for resetting said path to its initial amorphous condition, said source being selectively connectable to said electrodes for applying thereto for each reset operation a burst of reset voltage pulses spaced apart a fractional part of said recovery period and each of a value in excess of the tempoRary threshold voltage value, so reset current pulses are produced thereby each of which at least partially converts the crystalline filamentous path into a substantially amorphous condition.
Claim 17
Dependent Claim
57 words
The combination of claim 13 wherein the number of said reset voltage pulses and reset current pulses produced thereby are substantially in excess of the number needed to reset all of the resettable portions of the filamentous path to its maximum resistance condition to homogenize the same and prevent crystallization from developing therein under elevated temperature conditions.
Claim 18
Dependent Claim
77 words
The combination of claim 13 wherein said memory semiconductor material has the general formula: GeATeBXCYD where: A 5 to 60 atomic percent B 30 to 95 atomic percent C 0 to 10 atomic percent when X is Antimony (Sb) or Bismuth (Bi) or C 0 to 40 atomic percent when X is Arsenic (As) D 0 to 10 atomic percent when Y is Sulphur (S) or D 0 to 20 atomic percent when Y is Selenium (Se).
Claim 19
Dependent Claim
27 words
The combination of claim 14 wherein each reset current pulse is so low it only resets a small fraction of the filamentous path to an amorphous condition.
Claim 20
Dependent Claim
86 words
The combination of claim 15 wherein the amplitude of each of said reset current pulses in each burst of reset current pulses is a fraction substantially less than one-half the amplitude required substantially to fully reset the entire crystalline filament, the number of pulses in each burst of pulses being at least about 10, the spacing between said pulses is no greater than about 6 microseconds and the duration of each of said reset current pulses is a small fraction of the spacing between successive pulses.
Claim 21
Dependent Claim
26 words
The method of claim 1 wherein the spacing between said reset current pulses in said burst of reset current pulses is much less than 10 microseconds.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-11-24 | 1979-05-26 | 1979-11-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-11-24 | 1983-05-26 | 1983-11-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-11-24 | 1987-05-26 | 1987-11-25 | $7700.00 | Window Closed / Lapsed |