Nonvolatile semiconductor memory device and method of manufacturing the same

Claim 2

A nonvolatile semiconductor memory device with a vertical memory cell said vertical memory cell comprising: a channel portion vertically formed on a semiconductor substrate; a drain and a source formed at upper and lower positions of said channel portion to form a channel in said channel portion; a first floating gate formed on part of a side portion of said channel portion via a gate insulating film; a second floating gate formed on the side portion of said channel portion in a region without said first floating gate; and a control gate formed outside said first and second floating gates via an insulating isolation film, wherein one of said first floating gate and said second floating gate has a larger area in contact with said gate insulating film than the other of said first floating gate and said second floating gate.

Claim 3

A device according to claim 1 wherein one of said first floating gate and said second floating gate has an area twice that of the other of said first floating gate and said second floating gate.

Claim 4

A device according to claim 1 wherein said first floating gate and second floating gate partially overlap said drain region on the side portion of said channel portion via said insulating film.

Claim 5

A device according to claim 1 wherein said drain comprises a first drain formed on a side of said first floating gate and a second drain formed on a side of said second floating gate.

Claim 6

A device according to claim 1 wherein said source comprises a first source formed on a side of said first floating gate and a second source formed on a side of said second floating gate.

Claim 7

A device according to claim 1 wherein said second floating gate is sandwiched by said first floating gate and said semiconductor substrate.

Claim 8

A device according to claim 1, wherein said control gate is a single gate which overlaps said first and second floating gates via said insulating isolation film.

Claim 9

A nonvolatile semiconductor memory device with a vertical memory cell said vertical memory cell comprising: a channel portion vertically formed on a semiconductor substrate; a drain and a source formed at upper and lower positions of said channel portion to form a channel in said channel portion; a first floating gate formed on part of a side portion of said channel portion via a gate insulating film; a second floating gate formed on the side portion of said channel portion in a region without said first floating gate; and a control gate formed outside said first and second floating gates via an insulating isolation film, wherein one of said first floating gate and said second floating gate has a larger area than the other of said first floating gate and said second floating gate, and wherein said control gate comprises a first control gate formed outside said first floating gate via said insulating isolation film, and a second control gate formed outside said second floating gate via said insulating isolation film.

Claim 10

A nonvolatile semiconductor memory device with a vertical memory cell said vertical memory cell comprising: a channel portion vertically formed on a semiconductor substrate; a drain and a source formed at upper and lower positions of said channel portion to form a channel in said channel portion; a first floating gate formed on part of a side portion of said channel portion via a gate insulating film; a second floating gate formed on the side portion of said channel portion in a region without said first floating gate; and a control gate formed outside said first and second floating gates via an insulating isolation film, wherein one of said first floating gate and said second floating gate has a larger area than the other of said first floating gate and said second floating gate, and wherein said control gate comprises a first control gate formed outside said first floating gate via said insulating isolation film, and a second control gate formed outside said second floating gate via said insulating isolation film.

Claim 11

A nonvolatile semiconductor memory device with a vertical memory cell, said vertical memory cell comprising: a channel portion vertically formed on a semiconductor substrate; a drain and a source formed at upper and lower positions of said channel portion to form a channel in said channel portion; a first floating gate formed on part of a side portion of said channel portion via a gate insulating film, said first floating gate surrounding said channel portion; a second floating gate formed on the side portion of said channel portion in a region without said first floating gate, said second floating gate surrounding said channel portion in said region without said first floating gate; and a control gate formed outside said first and second floating gates via an insulating isolation film, wherein said second floating gate is sandwiched by said first floating gate and said semiconductor substrate, and wherein one of said first floating gate and said second floating gate has a larger area in contact with said gate insulating film than the other of said first floating gate and said second floating gate.

Claim 12

A nonvolatile semiconductor memory device with a vertical memory cell, said vertical memory cell comprising: a channel portion vertically formed on a semiconductor substrate; a drain and a source formed at upper and lower positions of said channel portion to form a channel in said channel portion; a first floating gate formed on part of a side portion of said channel portion via a gate insulating film, said first floating gate surrounding said channel portion; a second floating gate formed on the side portion of said channel portion in a region without said first floating gate, said second floating gate surrounding said channel portion in said region without said first floating gate; and a control gate formed outside said first and second floating gates via an insulating isolation film, wherein said second floating gate is sandwiched by said first floating gate and said semiconductor substrate, and wherein one of said first floating gate and said second floating gate has a larger area in contact with said gate insulating film than the other of said first floating gate and said second floating gate.

Claim 13

A device according to claim 9, wherein one of said first floating gate and said second floating gate has an area twice that of the other of said first floating gate and said second floating gate.

Claim 14

A device according to claim 9, wherein said first floating gate partially overlaps said drain region on the side portion of said channel portion via said insulating film.

Claim 15

A device according to claim 9, wherein said control gate is a single gate which overlaps said first and second floating gates via said insulating isolation film.