Combination film deposited switch unit and integrated circuits

Claim 2

A non-destructive memory matriX comprising: a semiconductor substrate having spaced parallel matrix conductor-forming regions of a given conductivity type formed within said semiconductor substrate and extending in spaced generally parallel relation to a first face of the substrate to form X or Y axis conductors of the matrix which are effectively insulated from one another; insulating layer means on said first face of said substrate; spaced parallel bands of conductive material deposited on said insulating layer means and extending generally transversely of said spaced parallel conductor-forming regions of said semiconductor substrate to form the other Y or X axis conductors of the matrix and crossing the X or Y axis conductors in spaced insulated relation thereto; and a memory device deposited adjacent each active cross-over point of the X and Y axis conductors of the matrix, each memory device including a deposited film of memory semiconductor material having spaced portions electrically coupled between the X and Y conductors of the associated cross-over point of the matrix and including means which makes the same triggerable into a stable relatively low resistance condition when the value of a voltage applied across said spaced portions exceeds a given voltage threshold level and which condition remains in such low resistance condition independently of the presence or absence of an applied voltage or current.

Claim 3

The memory matrix of claim 1 wherein each of said films of memory semiconductor material is resettable from a low resistance condition to a high resistance condition by the feeding of a given reset current pulse between said spaced portions thereof.

Claim 4

The memory matrix of claim 2 wherein each of said films of memory semiconductor material is resettable by a short current pulse exceeding a given value.

Claim 5

The memory matrix of claim 1 wherein said films of semiconductor memory material have bidirectional characteristics which conduct current substantially equally in either direction, and said voltage threshold level thereof is independent of the polarity of the applied voltage.

Claim 6

The memory matrix of claim 1 wherein there is provided read-out means for applying between any selected X axis conductor and any selected Y axis conductor a given voltage which effects current flow through the associated film of memory semiconductor material when it is in a low resistance condition.

Claim 7

The memory matrix of claim 2 wherein the X and Y axis conductors are to be addressed for set and reset operations, and there is provided in combination with said memory matrix, set means for applying between any selected X axis conductor and any selected Y axis conductor a set voltage which effects current flow in the associated film of memory semiconductor material by applying a voltage thereacross which exceeds its voltage threshold level; reset means for applying between any selected X axis conductor and any selected Y axis conductor a reset voltage which effects the flow of a reset current pulse through the associated film of memory semiconductor material when in its low resistance condition; and readout means for applying between any selected X axis conductor and any selected Y axis conductor a readout voltage which effects the flow of readout current when the associated film of memory semiconductor material is in its low resistance condition.

Claim 8

The memory matrix of claim 1 wherein there is integrally formed within the semiconductor substrate adjacent each active cross-over point of the matrix a doped P-N junction-forming region constituting an isolating means connected in series with the associated film of memory semiconductor material of the associated X and Y axis conductors involved, said isolating means normally isolating each cross-over point from the other crossover points.

Claim 9

The memory matrix of claim 7 wherein each of said P-N junction-forming regions of the semiconductor substrate is a single P-N junction forming diode.

Claim 10

The meMory matrix of claim 7 wherein each of said P-N junction forming regions of the semiconductor substrate is located respectively immediately adjacent the associated conductor-forming region thereof constituting the associated X or Y axis conductor of the matrix and between such conductor-forming region and said first face of the semiconductor substrate.

Claim 11

The memory matrix of claim 1 wherein each of said memory devices is a deposited film on said first face of said semiconductor substrate in alignment with the associated conductor-forming region constituting the associated X or Y axis conductor of the matrix.

Claim 12

The memory matrix of claim 7 wherein each film of memory semiconductor material is deposited upon said first face of said semiconductor substrate over the associated P-N junction forming region of the semiconductor substrate.

Claim 13

The memory matrix of claim 7 wherein each of said P-N junction forming regions forms the control and load electrodes of a transistor, two of said electrodes being connected in series with the associated memory device and the other electrode extending to an external terminal of the matrix.

Claim 14

The memory matrix of claim 1 wherein said insulating layer means has a plurality of apertures formed therein, each aperture being adjacent a crossover point of a pair of X and Y axis conductors and each memory device is electrically coupled to the associated X or Y axis conductors located within the substrate through its associated aperture.

Claim 15

The memory matrix of claim 1 wherein said semiconductor substrate is a silicon chip substantially of one conductivity type and said spaced parallel conductor-forming regions within said semiconductor substrate are of the opposite conductivity type and heavily doped to form a highly conductive region in the substrate.

Claim 16

The memory matrix of claim 1 wherein each memory device includes a first deposit of electrode-forming material making contact with one of said spaced portions of the associated film of memory semiconductor material and coupled to the associated X or Y axis conductor forming region within said substrate through said insulating layer means, and another deposit of electrode-forming material making contact with the other spaced portions of the associated film of memory semiconductor material

Claim 17

The memory matrix of claim 15 wherein said memory semiconductor material is a generally substantially amorphous material and the portion of said deposits of electrode-forming material in contact therewith being a substantially amorphous refractory material.

Claim 18

The memory matrix of claim 16 wherein said substantially amorphous refractory material is one of the group consisting of molybdenum, titanium, tantalum, niobium and refractory metal oxides, carbides and sulphides.

Claim 19

The memory matrix of claim 1 wherein each of said memory devices includes an insulating material with a pore formed extending therethrough, an electrode-forming material beneath the pore of said insulating material and coupled to the X or Y axis conductor formed within said semiconductor substrate, said film of memory semiconductor material being deposited within said pore to be in direct contact with said electrode-forming material.

Claim 20

The memory matrix of claim 18 wherein said deposit of memory semiconductor material of each memory device only partially fills said pore to a fraction of the depth of said pore, an electrode-forming conductive material filling the said pore, and the portion of the Y or X axis conductors deposited on said semiconductor substrate and associated with said memory device being connected to said electrode-forming material.

Claim 21

The memory matrix of claim 19 wherein said memory semiconductor material is a generally substantially amorphous material and the portion of said deposits of electrode-forming material in contact therewith being a substantially amorphous refractory material.

Claim 22

The memory matrix of claim 20 wherein said substantially amorphous refractory material is one of the group consisting of molybdenum, titanium, tantalum, noibium and refractory metal oxides, carbides and sulphides.

Claim 23

The memory matrix of claim 1 wherein there is provided an aperture within said insulating layer means adjacent each cross-over point of said X and Y axis conductors to expose a circuit element forming portion of said substrate, and there is provided for each memory device a first deposit of a conductive electrode-forming material on said insulating layer means below and contacting the associated deposit of memory semiconductor material to form a first electrode therefor; and a second deposit of conductive electrode-forming material over said deposit of semiconductor material and electrically contacting the same to form a second electrode for the memory semiconductor material; and a portion of said first deposit of conductive electrode-forming material being overlaid by a layer of readily oxidizable material which enters the associated aperture to make electrical connection with said circuit element forming portion of said substrate.

Claim 24

The memory matrix of claim 22 wherein said deposits of electrode-forming material are a refractory material.

Claim 25

The memory matrix of claim 23 wherein each deposit of said refractory material is in an amorphous condition at least at the surface in direct contact with said memory semiconductor material.

Claim 26

The memory matrix of claim 1 wherein there is provided an aperture within said insulating layer means adjacent each cross-over point of said X and Y axis conductors to expose a portion of said semiconductor substrate, a first deposit of a refractory conductive material on said insulating layer means around each of said apertures, a second deposit of a non-refractory conductive material over each of said first deposit of refractory conductive material except for a small electrode-forming portion of said first deposit of conductive material which is free of said second deposit of non-refractory conductive material, each second deposit of conductive material extending into the associate aperture to make electrical contact with the exposed portion of said semiconductor substrate, an electrode-forming portion extending from each of the said Y or X axis conductors formed over said semiconductor substrate and spaced from the electrode forming portion of said first deposit of conductive material, and said memory semiconductor material of each memory device being deposited within the space between the said opposing electrode forming portions.

Claim 27

A memory matrix array comprising: a support base made of semiconductor material and having a plurality of X axis conductors, a plurality of Y axis conductors insulated from and extending transversely of said X axis conductors to form insulated cross-over points of the matrix, memory switch device-forming material and isolating device-forming material associated with each active cross-over point of said X and Y axis conductors and connected in series between the same, the memory switch device-forming material associated with each active cross-over point being a deposit on said side of said support base adjacent the associated cross-over point, the memory switch device-forming material including means making the same alterable by application of a voltage which exceeds a threshold level from a stable condition of relatively low resistance which persists indefinitely after the applied voltage is removed therefrom until reset to a high resistance, the isolating device-forming material associated with each crossover point being a doped region of said semiconductor material of the support base located adjacent the associated cross-over point and which region includes means imparting to the same a conductive condition where it acts as a low resistance to a desired flow of current through the memory switch device-forming material of the associated cross-over point and a non-conductive condition where it isolates the associated Cross-over point from the other cross-over points when the memory switch device-forming material thereat is in a low resistance condition, one of said plurality of X or Y axis conductors being located on the side of said support base on which said memory switch device-forming material is deposited and the other of same being on the side of said doped regions of the semiconductor support base remote from said switch device-forming memory material.

Claim 28

A memory matrix array comprising: a support base made of semiconductor material and having a plurality of X axis conductors, a plurality of Y axis conductors insulated from and extending transversely of said X axis conductors to form insulated cross-over points of the matrix, memory switch device-forming material and isolating device-forming material associated with each active cross-over point of said X and Y axis conductors and connected in series between the same, the memory switch device-forming material associated with each active cross-over point being a deposit on said side of said support base adjacent the associated cross-over point, the memory switch device-forming material including means making the same alterable by application of a voltage which exceeds a threshold level from a stable condition of relatively low resistance which persists indefinitely after the applied voltage is removed therefrom until reset to a high resistance, the isolating device-forming material associated with each crossover point being a doped region of said semiconductor material of the support base located adjacent the associated cross-over point and which region includes means imparting to the same a conductive condition where it acts as a low resistance to a desired flow of current through the memory switch device-forming material of the associated cross-over point and a non-conductive condition where it isolates the associated Cross-over point from the other cross-over points when the memory switch device-forming material thereat is in a low resistance condition, one of said plurality of X or Y axis conductors being located on the side of said support base on which said memory switch device-forming material is deposited and the other of same being on the side of said doped regions of the semiconductor support base remote from said switch device-forming memory material.

Claim 29

The memory matrix of claim 26 wherein said one plurality of the X or Y axis conductors are doped regions within the support base.

Claim 30

A non-destructive memory matrix comprising: a substrate having spaced parallel matrix conductor-forming regions formed within said substrate and extending in spaced generally parallel relation to a first face of the substrate to form X or Y axis conductors of the matrix which are effectively insulated from one another; an isolating element formed within the substrate adjacent each active cross-over point of the X and Y axis conductors; insulating layer means on said first face of said substrate; spaced parallel bands of conductive material deposited on said insulating layer means and extending generally transversely of said spaced parallel conductor-forming regions of said semiconductor substrate to form the other Y or X axis conductors of the matrix and crossing the X or Y axis conductors in spaced insulated relation thereto; and a memory device deposited on the substrate beneath the Y or X axis conductor adjacent each active cross-over point, the isolating element and memory device of each cross-over point being connected in series between the X and Y axis conductors thereof, each memory device including means making the same alterable by application of a voltage which exceeds a threshold level from a stable condition of relatively high resistance to a stable condition of relatively low resistance which persists indefinitely after the applied voltage is removed therefrom until reset to a high resistance, each isolating element having means imparting thereto a conductive condition where it acts as a low resistance to a desired flow of current through the associated memory switch and a non-conductive condition where it isolates the associated cross-over point from the other cross-over points when the body of memory switch device-forming material thereat is in a low resistance condition.

Claim 31

A non-destructive memory matrix comprising: a substrate having spaced parallel matrix conductor-forming regions formed within said substrate and extending in spaced generally parallel relation to a first face of the substrate to form X or Y axis conductors of the matrix which are effectively insulated from one another; an isolating element formed within the substrate adjacent each active cross-over point of the X and Y axis conductors; insulating layer means on said first face of said substrate; spaced parallel bands of conductive material deposited on said insulating layer means and extending generally transversely of said spaced parallel conductor-forming regions of said semiconductor substrate to form the other Y or X axis conductors of the matrix and crossing the X or Y axis conductors in spaced insulated relation thereto; and a memory device deposited on the substrate beneath the Y or X axis conductor adjacent each active cross-over point, the isolating element and memory device of each cross-over point being connected in series between the X and Y axis conductors thereof, each memory device including means making the same alterable by application of a voltage which exceeds a threshold level from a stable condition of relatively high resistance to a stable condition of relatively low resistance which persists indefinitely after the applied voltage is removed therefrom until reset to a high resistance, each isolating element having means imparting thereto a conductive condition where it acts as a low resistance to a desired flow of current through the associated memory switch and a non-conductive condition where it isolates the associated cross-over point from the other cross-over points when the body of memory switch device-forming material thereat is in a low resistance condition.

Claim 32

The memory matrix of claim 28 wherein each memory device and associated isolating element are located in alignment with the associated cross-over point.

Claim 33

The memory matrix of claim 1 wherein said parallel matrix conductor-forming regions of a given conductivity type in the semiconductor substrate are separated by doped regions of semiconductor material of opposite type which electrically isolate the same from one another.

Claim 34

The memory matrix of claim 30 wherein said parallel matrix conductor-forming regions in the substrate are spaced from said first face thereof, and said semiconductor substrate between each such matrix conductor-forming region and each deposited memory device at each active matrix cross-over point is doped to form at least one P-N junction constituting at least part of an isolating means connected in series between the associated memory device and matrix conductor-forming region.