Memory matrix having serially connected threshold and memory switch devices at each cross-over point

Claim 1

A memory matrix including X and Y axis conductors forming rows and columns of conductors to be addressed for set, reset and readout operations, comprising in combination, first and second series connected switch devices coupled between each active crossover point of the X and Y conductors, each first switch device being a threshold switch device which has a threshold voltage value, a relatively high resistance condition and a relatively large voltage drop thereacross in the high resistance condition for voltages near the threshold voltage value applied thereto, which is switched to a relatively low resistance condition when the voltage applied thereto reaches the threshold voltage value, which has a relatively small voltage drop thereacross in the low resistance condition which is a minor fraction of the aforesaid voltage drop thereacross in the high resistance condition, and which remains in the low resistance condition until the instantaneous value of the current therethrough drop below a given holding value whereupon it switches back to the high resistance condition, each second switch device being a memory switch device which has a threshold voltage value, a relatively high resistance condition and a relatively large voltage drop thereacross in the high resistance condition for voltages near the threshold voltage value applied thereto, which is switched to a relatively low resistance condition when the voltage applied thereto reaches the threshold voltage value, which has a relatively small voltage drop thereacross in the low resistance condition which is a minor fraction of the aforesaid voltage drop thereacross in the high resistance condition, which remains in the low resistance condition independently of the presence or absence of an applied voltage until reset to the high resistance condition by feeding a reset current pulse of a given value therethrough, the thresholD voltage value of the threshold switch device being substantially less than that of the memory switch device and the resistance value of the high resistance condition of the threshold switch device being many times greater than that of the memory switch device, set means for applying between any selected X conductor and any selected Y conductor of an active crossover point a set voltage pulse of sufficient value to drive first the serially connected threshold switch device and then immediately the memory switch device associated with the selected crossover point into their low resistance conditions and to switch the threshold switch device back to its high resistance condition upon termination of the set voltage pulse, reset means for applying between any selected X conductor and any selected Y conductor of an active crossover point a reset current pulse having sufficient voltage to drive the threshold switch device associated with the selected crossover point to its low resistance condition when the associated memory switch device is in its low resistance condition to feed a reset current pulse through the memory switch device to its high resistance condition, and readout means for applying between any selected X conductor and any selected Y conductor a readout current pulse having sufficient voltage to drive the threshold switch device to its low resistance condition when the associated memory switch device is in its low resistance condition to feed a readout current pulse which is less than said reset current pulse through the memory switch device in its low resistance condition for readout purposes.