US5536968A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polysilicon fuse array structure for integrated circuits
Assignee: MagnaChip Semiconductor Ltd
•
Filing: 1994-08-16
•
Granted: 1996-07-16
•
Expires: 2014-08-16
Abstract
Abstract A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon fuse element within the array connects a first electrical conductor residing in the first patterned signal layer with a second electrical conductor residing in the second patterned signal layer. The polysilicon fuse element is in the form of a narrow strip and is folded in order to cause a current flowing through the clement to crowd, lowering the amount of current required to heat the fuse element to its melting point, i.e. the threshold current. The PROM is programmed by passing a threshold current through selected fuse elements.
Inventors
- 👤 Harold S. Crafts
- 👤 William W. McKinley
- 👤 Mark O. Scaggs
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:31
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10B; H10B20/00; H10B20/20
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
119 words
A semiconductor structure comprising: a first electrical conductor; a second electrical conductor electrically separated from said first electrical conductor; a polysilicon strip connecting said first and second electrical conductors and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor; a first patterned signal layer, said first electrical conductor and said polysilicon strip residing in said first patterned signal layer; and a second patterned signal layer electrically separated from said first patterned signal layer, said second electrical conductor residing in said second patterned signal layer.
Claim 2
Dependent Claim
119 words
A semiconductor structure comprising: a first electrical conductor; a second electrical conductor electrically separated from said first electrical conductor; a polysilicon strip connecting said first and second electrical conductors and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor; a first patterned signal layer, said first electrical conductor and said polysilicon strip residing in said first patterned signal layer; and a second patterned signal layer electrically separated from said first patterned signal layer, said second electrical conductor residing in said second patterned signal layer.
Claim 3
Dependent Claim
24 words
The semiconductor structure according to claim 1, further comprising: a plated via connecting said second electrical conductor to one end of said polysilicon strip.
Claim 4
Dependent Claim
137 words
A semiconductor structure comprising: a first electrical conductor; a second electrical conductor electrically separated from said first electrical conductor: a polysilicon strip connecting said first and second electrical conductors and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor: a first input drive connected to said first electrical conductor for selectively coupling said first electrical conductor to a first reference voltage; and a second input drive connected to said second electrical conductor for selectively coupling said second electrical conductor to a second reference voltage; whereby a programming current can be established between said first and second reference voltages for opening said polysilicon strip.
Claim 5
Dependent Claim
137 words
A semiconductor structure comprising: a first electrical conductor; a second electrical conductor electrically separated from said first electrical conductor: a polysilicon strip connecting said first and second electrical conductors and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor: a first input drive connected to said first electrical conductor for selectively coupling said first electrical conductor to a first reference voltage; and a second input drive connected to said second electrical conductor for selectively coupling said second electrical conductor to a second reference voltage; whereby a programming current can be established between said first and second reference voltages for opening said polysilicon strip.
Claim 6
Dependent Claim
55 words
The semiconductor structure according to claim 3, further comprising: a pull-up resistor connected between said second voltage source and said second electrical conductor; and a sense amplifier connected to said second electrical conductor for sensing the voltage potential of said second electrical conductor when said first electrical conductor is coupled to said first reference voltage.
Claim 7
Dependent Claim
33 words
The semiconductor structure according to claim 4, further comprising: a diode connected between said polysilicon strip and said first electrical conductor for blocking current flow from said first conductor into said polysilicon strip.
Claim 8
Dependent Claim
15 words
The semiconductor structure according to claim 1, wherein said structure is implemented in CMOS technology.
Claim 9
Dependent Claim
115 words
A programmable read only memory (PROM) comprising: a first patterned signal layer; a second patterned signal layer, said second patterned signal layer being electrically separated from said first patterned signal layer; a plurality of fuse structures, each one of said fuse structures comprising a polysilicon strip connecting a first electrical conductor residing in said first patterned signal layer with a second electrical conductor residing in said second patterned signal layer and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor.
Claim 10
Dependent Claim
115 words
A programmable read only memory (PROM) comprising: a first patterned signal layer; a second patterned signal layer, said second patterned signal layer being electrically separated from said first patterned signal layer; a plurality of fuse structures, each one of said fuse structures comprising a polysilicon strip connecting a first electrical conductor residing in said first patterned signal layer with a second electrical conductor residing in said second patterned signal layer and forming a fuse between said first and second electrical conductors, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor.
Claim 11
Dependent Claim
33 words
The PROM according to claim 7, wherein: said plurality of fuse structures are arranged in an array forming at least one row of fuse structures and at least one column of fuse structures.
Claim 12
Dependent Claim
132 words
A programmable read only memory (PROM) comprising: a first patterned signal layer including at least one electrical conductor oriented in a first direction; a second patterned signal layer being electrically separated from said first signal layer, said second patterned signal layer including at least one electrical conductor oriented in a second direction; and a plurality of fuse structures, each one of said fuse structures comprising a polysilicon strip connecting a first electrical conductor residing in said first patterned signal layer with a second electrical conductor residing in said second patterned signal layer and forming a fuse there between, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor.
Claim 13
Dependent Claim
132 words
A programmable read only memory (PROM) comprising: a first patterned signal layer including at least one electrical conductor oriented in a first direction; a second patterned signal layer being electrically separated from said first signal layer, said second patterned signal layer including at least one electrical conductor oriented in a second direction; and a plurality of fuse structures, each one of said fuse structures comprising a polysilicon strip connecting a first electrical conductor residing in said first patterned signal layer with a second electrical conductor residing in said second patterned signal layer and forming a fuse there between, said polysilicon strip including a narrow middle section, whereby said fuse will be opened by a current which is passed from said first electrical conductor through said polysilicon strip into said second electrical conductor.
Claim 14
Dependent Claim
101 words
The PROM according to claim 9, wherein: said plurality of fuse structures are arranged in an array comprising at least one row of fuse structures oriented in said first direction and at least one column of fuse structures oriented in said second direction; each row of fuse structures is associated with one of said electrical conductors residing in said first patterned signal layer; each column of fuse structures is associated with one of said electrical conductors residing in said second patterned signal layer; and each one of said fuse structures connects the electrical conductors associated with its corresponding row and column.
Claim 15
Dependent Claim
124 words
The PROM according to claim 10, further comprising: an address input driver corresponding to each said electrical conductor residing in said first patterned signal layer for selectively coupling its corresponding electrical conductor to a first reference voltage; and a data input driver corresponding to each said electrical conductor residing in said second patterned signal layer for selectively coupling its corresponding electrical conductor to a second reference voltage; whereby a programming current path can be established between said first and second reference voltages, said current path including a selected one of said electrical conductors residing in said first patterned signal layer and a selected one of said electrical conductors residing in said second patterned signal layer, and the polysilicon strip connecting said selected electrical conductors.
Claim 16
Dependent Claim
74 words
The PROM according to claim 11, further comprising: a pull-up resistor connected between said second reference voltage and each said electrical conductor residing in said second patterned signal layer; and a sense amplifier connected to each said electrical conductor residing in said second patterned signal layer for sensing the voltage potential of said second electrical conductor when an electrical conductor residing in said first patterned signal layer is coupled to said first reference voltage.
Claim 17
Dependent Claim
24 words
The semiconductor structure according to claim 12, wherein: each one of said fuse structures includes a diode connected in series with said polysilicon strip.
References Cited (Backward Citations)
US4045310A
Cited
JPS57139958A
Cited
JPS61283163A
Cited
JPS63308361A
Cited
JPH03124047A
Cited
US5053999A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-16 | 2000-01-15 | 2000-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-16 | 2004-01-15 | 2004-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-16 | 2008-01-15 | 2008-07-16 | $7700.00 | Window Closed / Lapsed |