US3629863A — Film deposited circuits and devices therefor

Claim 1

Independent Claim 294 words

A memory matrix comprising an insulating base, parallel bands of X or Y axis conductors deposited on one side of said insulating base, said insulating base including parallel bands of Y or X axis conductors crossing said X or Y axis conductors and insulating material interposed between the X anD Y axis conductors at the crossover points to insulate the same, a pair of series connected switch devices coupled between the X and Y axis conductors of each active crossover point, at least one of the switch devices including a deposited layer of semiconductor material located adjacent each crossover point of said X and Y axis conductors, the other switch device including a deposited layer of semiconductor material located adjacent each crossover point of said X and Y axis conductors, the deposited layer of semiconductor material of one of the switch devices of each pair of switch devices being a threshold switch device-forming material having a relatively high-resistance condition when the value of the voltage applied thereto is below a first voltage threshold level and is switched to a relatively low-resistance condition when the value of the voltage applied thereto reaches said first voltage threshold level which low-resistance condition remains until the value of the current therethrough drops below a given holding value, and the deposited layer of semiconductor material of the other switch device of each pair of switch devices being a memory switch device-forming material which is triggered into a stable relatively low-resistance condition when the value of the voltage applied thereto exceeds a second voltage threshold level and which condition remains in such lowresistance condition independently of the presence or absence of an applied voltage until reset to a high-resistance condition by the feeding of a given reset current pulse therethrough.

Claim 2

Dependent Claim 294 words

A memory matrix comprising an insulating base, parallel bands of X or Y axis conductors deposited on one side of said insulating base, said insulating base including parallel bands of Y or X axis conductors crossing said X or Y axis conductors and insulating material interposed between the X anD Y axis conductors at the crossover points to insulate the same, a pair of series connected switch devices coupled between the X and Y axis conductors of each active crossover point, at least one of the switch devices including a deposited layer of semiconductor material located adjacent each crossover point of said X and Y axis conductors, the other switch device including a deposited layer of semiconductor material located adjacent each crossover point of said X and Y axis conductors, the deposited layer of semiconductor material of one of the switch devices of each pair of switch devices being a threshold switch device-forming material having a relatively high-resistance condition when the value of the voltage applied thereto is below a first voltage threshold level and is switched to a relatively low-resistance condition when the value of the voltage applied thereto reaches said first voltage threshold level which low-resistance condition remains until the value of the current therethrough drops below a given holding value, and the deposited layer of semiconductor material of the other switch device of each pair of switch devices being a memory switch device-forming material which is triggered into a stable relatively low-resistance condition when the value of the voltage applied thereto exceeds a second voltage threshold level and which condition remains in such lowresistance condition independently of the presence or absence of an applied voltage until reset to a high-resistance condition by the feeding of a given reset current pulse therethrough.

Claim 3

Dependent Claim 25 words

The memory matrix of claim 1 wherein the reset current of each of said memory switch device is a current pulse exceeding a given value.

Claim 4

Dependent Claim 45 words

The memory matrix of claim 1 wherein said threshold and switch devices are bidirectional devices which conduct current in either direction and said threshold voltage levels and reset current pulse are independent of the polarity of the applied voltage or the direction of current flow.

Claim 5

Dependent Claim 188 words

The memory matrix of claim 1 wherein there is provided set means for applying between any selected X axis conductor and any selected Y axis conductor of an active crossover point a set voltage which drives both the threshold switch device and the memory switch device associated with the selected crossover point into their low-resistance condition; reset means for applying between any selected X axis conductor and any selected Y axis conductor of an active crossover point a reset voltage which drives the threshold switch device associated with the selected crossover point to its low-resistance condition when the associated memory switch device is in its low-resistance condition and feeds a reset current pulse through the memory switch device; and readout means for applying between any selected X axis conductor and any selected Y axis conductor a readout voltage which exceeds the threshold level of the associated threshold switch device and is of only sufficient value to drive the associated threshold switch device to its low-resistance condition if the associated memory switch device is in its low-resistance condition, to produce a current flow other than the reset current pulse.

Claim 6

Dependent Claim 26 words

The memory matrix of claim 4 wherein the applied readout voltage for a readout operation is operable at a given magnitude independently of the polarity thereof.

Claim 7

Dependent Claim 95 words

In combination with an insulating base having a conductive deposit thereon, a deposited film semiconductor device carried by said insulating base, said device including a layer of insulating material applied over said conductive deposit, said layer of insulating material having a small hole extending therethrough, a body of semiconductor material overlying said layer of insulating material and extending into said hole where it makes contact with said conductive deposit on said insulating base over an area limited by the size of said hole, and a conductive deposit over the outer surface of said semiconductor material.

Claim 8

Dependent Claim 95 words

In combination with an insulating base having a conductive deposit thereon, a deposited film semiconductor device carried by said insulating base, said device including a layer of insulating material applied over said conductive deposit, said layer of insulating material having a small hole extending therethrough, a body of semiconductor material overlying said layer of insulating material and extending into said hole where it makes contact with said conductive deposit on said insulating base over an area limited by the size of said hole, and a conductive deposit over the outer surface of said semiconductor material.

Claim 9

Dependent Claim 53 words

The combination of claim 6 wherein said semiconductor material has a high-resistance condition where it is substantially nonconductive and is switched to a low-resistance condition where it conducts current in a filamentous path through the semiconductor material when a voltage is applied across said semiconductor material which exceeds a given threshold voltage level.

Claim 10

Dependent Claim 30 words

The combination of claim 7 wherein said body of semiconductor material conducts current in either direction and said threshold voltage level is independent of the polarity of the applied voltage.

Claim 11

Dependent Claim 280 words

A switching and memory matrix array comprising: a support base including a plurality of parallel X or Y axis conductors deposited on said support base; a plurality of discrete first layers of semiconductor material deposited on said support base adjacent said plurality of X or Y axis conductors and electrically coupled thereto and arranged in substantially parallel rows; a plurality of discrete second layers of semiconductor material deposited on said support base and respectively connected to and adjacent said plurality of discrete first layers of semiconductor material and respectively electrically connected in series therewith; and said support base having a plurality of Y or X axis conductors insulated from and extending transversely of the X or Y axis conductors and connected to said plurality of discrete second layers of semiconductor material, one of said discrete layers of said semiconductor material being of a memory switch device-forming type which is triggered into a stable relatively low-resistance condition when the value of the voltage applied thereto exceeds a first voltage threshold level and which condition remains in such low-resistance condition independently of the presence or absence of an applied voltage until reset to a high-resistance condition by the feeding of a given reset current pulse therethrough, and the other of said discrete layers of semiconductor material being of the threshold switch device-forming type having a relatively high-resistance condition when the value of the voltage applied thereto is below a second voltage threshold level and is switched to a relatively low-resistance condition when the value of the voltage applied thereto reaches said second voltage threshold level which low-resistance condition remains until the value of the current therethrough drops below a given holding current.

Claim 12

Dependent Claim 280 words

A switching and memory matrix array comprising: a support base including a plurality of parallel X or Y axis conductors deposited on said support base; a plurality of discrete first layers of semiconductor material deposited on said support base adjacent said plurality of X or Y axis conductors and electrically coupled thereto and arranged in substantially parallel rows; a plurality of discrete second layers of semiconductor material deposited on said support base and respectively connected to and adjacent said plurality of discrete first layers of semiconductor material and respectively electrically connected in series therewith; and said support base having a plurality of Y or X axis conductors insulated from and extending transversely of the X or Y axis conductors and connected to said plurality of discrete second layers of semiconductor material, one of said discrete layers of said semiconductor material being of a memory switch device-forming type which is triggered into a stable relatively low-resistance condition when the value of the voltage applied thereto exceeds a first voltage threshold level and which condition remains in such low-resistance condition independently of the presence or absence of an applied voltage until reset to a high-resistance condition by the feeding of a given reset current pulse therethrough, and the other of said discrete layers of semiconductor material being of the threshold switch device-forming type having a relatively high-resistance condition when the value of the voltage applied thereto is below a second voltage threshold level and is switched to a relatively low-resistance condition when the value of the voltage applied thereto reaches said second voltage threshold level which low-resistance condition remains until the value of the current therethrough drops below a given holding current.

Claim 13

Dependent Claim 95 words

The memory matrix of claim 1 wherein said deposited layer of semiconductor material forming said at least one of the switch devices of each crossover point is deposited over the portion of the associated X or Y axis conductor involved between the associated Y or X axis conductor and the immediately adjacent Y or X axis conductor and the deposited layer of semiconductor material of the other of said switch devices is deposited over the portion of the associated Y axis conductor between the associated X axis conductor and the immediately adjacent X axis conductor.

Claim 14

Dependent Claim 75 words

The switching and memory matrix array of claim 9 wherein said plurality of discrete first layers of semiconductor material are deposited on each of the said plurality of X or Y axis conductors, said plurality of discrete second layers of semiconductor material are deposited over said plurality of discrete first layers of semiconductor material and said plurality of Y or X axis conductors are deposited on said plurality of discrete second layers of semiconductor material.

Claim 15

Dependent Claim 61 words

The switching and memory matrix array of claim 11 further including an apertured insulator deposited between each of said plurality of discrete first layers of semiconductor material and each of said plurality of discrete second layers of semiconductor material such that electrical contact is made between each of said first and second layers through the aperture formed in their associated insulator.

Claim 16

Dependent Claim 27 words

The switching matrix of claim 1 wherein all of said bands of X and Y axis cOnductors are deposits on the same side of said insulating base.

Claim 17

Dependent Claim 50 words

The switching and memory matrix of claim 9 wherein said first layer of semiconductor material of each crossover point is located respectively in alignment with said X or Y axis conductor thereat, and said second layer of semiconductor material thereof is located respectively in alignment with the other of same.

Claim 18

Dependent Claim 262 words

A memory matrix comprising: a matrix-forming unit including a nonconducting supporting base; a first group of parallel bands of conductors; a second group of parallel bands of conductors deposited as a film on one side of said base and arranged so that each band in said second group crosses each band in said first group forming a matrix of crossover points; memory means located at or adjacent each of said crossover points for selectively connecting and disconnecting the two bands of conductors crossing at each said crossover point, each memory means being a film of semiconductor memory material deposited on said one side of said base and having at least a stable relatively high-resistance condition and a stable relatively low-resistance condition and being resettably switched into said stable low resistance condition when the value of voltage applied thereto exceeds a certain threshold level and which remains in such low-resistance condition even in the absence of an applied voltage or current until reset into said high-resistance condition in response to a certain momentary reset signal; and isolating means at or adjacent each of said crossover points connected in series circuit with said memory means thereat between the two associated bands of crossing conductors for isolating said memory means thereat from other memory means associated with other crossover points, wherein an applied voltage for altering any selected memory means from said high to said low-resistance condition or a reset signal for resetting the same to said high-resistance condition are not erroneously short circuited through memory means in said low-resistance condition at different crossover points.

Claim 19

Dependent Claim 262 words

A memory matrix comprising: a matrix-forming unit including a nonconducting supporting base; a first group of parallel bands of conductors; a second group of parallel bands of conductors deposited as a film on one side of said base and arranged so that each band in said second group crosses each band in said first group forming a matrix of crossover points; memory means located at or adjacent each of said crossover points for selectively connecting and disconnecting the two bands of conductors crossing at each said crossover point, each memory means being a film of semiconductor memory material deposited on said one side of said base and having at least a stable relatively high-resistance condition and a stable relatively low-resistance condition and being resettably switched into said stable low resistance condition when the value of voltage applied thereto exceeds a certain threshold level and which remains in such low-resistance condition even in the absence of an applied voltage or current until reset into said high-resistance condition in response to a certain momentary reset signal; and isolating means at or adjacent each of said crossover points connected in series circuit with said memory means thereat between the two associated bands of crossing conductors for isolating said memory means thereat from other memory means associated with other crossover points, wherein an applied voltage for altering any selected memory means from said high to said low-resistance condition or a reset signal for resetting the same to said high-resistance condition are not erroneously short circuited through memory means in said low-resistance condition at different crossover points.

Claim 20

Dependent Claim 31 words

The memory matrix of claim 15 wherein there is provided insulating material deposited on said one side of said base at said crossover points which provides insulation between said crossover points.

Claim 21

Dependent Claim 45 words

The memory matrix of claim 15 wherein said film of semiconductor memory material forming the memory means of each crossover point is a film of material physically separated from other films of semiconductor memory material forming the memory means at the other respective crossover points.

Claim 22

Dependent Claim 46 words

The memory matrix of claim 15 wherein said deposited film of semiconductor memory material forming each said memory means is resettable to said relatively high-resistance condition when said reset signal is of the same polarity as the voltage which switches the same to said low-resistance condition.

Claim 23

Dependent Claim 75 words

The memory matrix of claim 15 wherein said deposited film of semiconductor memory material forming the memory means associated with each crossover point forms a bidirectional memory device which can conduct current in either direction, and wherein said threshold level is independent of the polarity of the applied voltage or the direction of current flow therethrough, and said reset signal can be of either polarity to reset said semiconductor material to said relatively high-resistance condition.

Claim 24

Dependent Claim 29 words

The memory matrix of claim 15 wherein the memory means and isolating means associated with each crossover point are in alignment with one another and the associated crossover point.

Claim 25

Dependent Claim 35 words

The memory matrix of claim 15 wherein said memory means and isolating means associated with each crossover point are located one over the other between the associated crossing bands of conductors at the crossover point.

Claim 26

Dependent Claim 59 words

The memory matrix of claim 15 wherein said isolating means and first group of parallel bands of conductors form a single integral body with said base, said deposited memory means and second group of parallEl bands of conductors being deposited with said second group of parallel bands of conductors passing over said first group of parallel bands of conductors.

Claim 27

Dependent Claim 23 words

The memory matrix of claim 22 wherein both groups of crossing bands of conductors are deposits on the same side of said base.

Claim 28

Dependent Claim 30 words

The memory matrix of claim 23 wherein said memory means and isolating means at each crossover point are both deposits of semiconductor material on said same side of the base.

Claim 29

Dependent Claim 43 words

The memory matrix of claim 15 wherein said memory means and isolating means at each crossover point are respectively located at points adjacent to but spaced from the associated crossover point and respectively in alignment with the respective bands of conductors crossing thereat.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1974-12-20	1975-06-21	1975-12-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1978-12-20	1979-06-21	1979-12-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1982-12-20	1983-06-21	1983-12-21	$7700.00	Window Closed / Lapsed

Film deposited circuits and devices therefor

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