Writing a read-only memory while protecting nonselected elements

Claim 2

In combination: a plurality of impedance elements interconnected to form multiple bilateral current paths between terminals of any one of said elements, said paths including row and column circuits of a matrix in which said elements are cross-point circuits interconnecting said row and column circuits, means driving through at least a selected one of said elements a current of sufficient magnitude to destroy such element, a selected element interconnecting a selected row circuit and a selected column circuit, said driving means comprising means coupling each selected column circuit to a voltage reference, and means applying to each selected row circuit a first voltage with respect to said voltage reference, means biasing all nonselected ones of said elements in said paths between terminals of said selected element to limit current in each such path to a magnitude that is insufficient to destroy any of said nonselected elements, said biasing means cooperating with said driving means and further including means biasing nonselected column circuits to a second voltage with respect to said voltage reference, said second voltage being smaller than said first voltage, and means biasing nonselected row circuits to a third voltage with respect to said voltage reference, said third voltage being smaller than said second voltage.

Claim 3

In combination: an impedance matrix having row and column circuits orthogonally arranged and interconnected at intersections thereof by respective impedance elements, each of said elements having a predetermined destruct voltage magnitude limit at which current through the element causes destruction thereof, means applying across a selected row circuit and a selected column circuit a voltage at least equal to said voltage limit for driving destructive current through the one of said impedance elements interconnecting such row and column circuit, means simultaneously biasing nonselected ones of said row and column circuits to voltage magnitudes which are less than said voltage limit for thereby limiting the magnitude of voltage appearing across every nonselected one of said impedance elements to a predetermined fraction of said destruct voltage magnitude limit, and means programming operation of said biasing means and said applying means to operate them in a predetermined sequence for thereby limiting voltage magnitude across said nonselected impedance elements, said programming means comprising means biasing each of said row circuits to approximately one-third of said voltage across said selected row and column circuits, means thereafter biasing said column circuits to either a reference voltage or a voltage which is approximately two-thirds of said voltage across said selected row and column circuits in accordance with predetermined information to be written into cross-point impedance elements connected to one of said row circuits, said column circuits which are biased to said reference voltage being selected column circuits, and means biasing said selected row circuit to a voltage at least equal to said voltage limit.

Claim 4

In combination: an impedance matrix having row and column circuits orthogonally arranged and interconnected at intersections thereof by respective impedance elements, each of said elements having a predetermined destruct voltage magnitude limit at which current through the element causes destruction thereof, means applying across a selected row circuit and a selected column circuit a voltage at least equal to said voltage limit for driving destructive current through the one of said impedance elements interconnecting such row and column circuit, means simultaneously biasing nonselected ones of said row and column circuits to voltage magnitudes which are less than said voltage limit for thereby limiting the magnitude of voltage appearing across every nonselected one of said impedance elements to a predetermined fraction of said destruct voltage magnitude limit, and means programming operation of said biasing means and said applying means to operate them in a predetermined sequence for thereby limiting voltage magnitude across said nonselected impedance elements, said programming means comprising means biasing each of said row circuits to approximately one-third of said voltage across said selected row and column circuits, means thereafter biasing said column circuits to either a reference voltage or a voltage which is approximately two-thirds of said voltage across said selected row and column circuits in accordance with predetermined information to be written into cross-point impedance elements connected to one of said row circuits, said column circuits which are biased to said reference voltage being selected column circuits, and means biasing said selected row circuit to a voltage at least equal to said voltage limit.

Claim 5

The combination in accordance with claim 2 in which: said impedance elements are resistors of substantially the same magnitude throughout said matrix.