US5391518A
Expired / Lapsed
US
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Method of making a field programmable read only memory (ROM) cell using an amorphous silicon fuse with buried contact polysilicon and metal electrodes
Assignee: NXP BV
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Filing: 1993-09-24
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Granted: 1995-02-21
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Expires: 2013-09-24
Abstract
Abstract To fabricate a programmable read only memory cell an implant region is formed within a substrate. A first conductive layer is formed over the substrate. For example, the first conductive layer is polysilicon. The first conductive layer is etched to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for a transistor. Atoms of a first conductivity type are implanted into the substrate into a first source/drain region on a first side of the gate region and into a second source/drain region on a second side of the gate region. The second source/drain region is electrically coupled to the implant region. An insulating layer is formed over the first electrode. The insulating layer has a link contact which extends to the first electrode region. The insulating layer also has a contact hole extending to the first source drain region. An amorphous silicon layer is formed within the link contact and in contact with the first electrode. A metal layer is deposited. The metal layer is etched to form a second electrode in contact with the amorphous silicon layer and electrically separated from the first electrode by the amorphous silicon layer, and to form a metal contact to the first source/drain region through the contact hole.
Inventors
- 👤 Bharat Bhushan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:00
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/20; H10B20/25
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
217 words
A method for fabricating a programmable read only memory cell, the method comprising the steps of: (a) forming an implant region within a substrate; (b) forming a first conductive layer over the substrate; (c) selectively etching the first conductive layer to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for a transistor; (d) implanting atoms of a first conductivity type into the substrate into a first source/drain region on a first side of the gate region and into a second source/drain region on a second side of the gate region, wherein the second source/drain region is electrically coupled to the implant region; (e) forming an insulating layer over the first electrode, the insulating layer having a link contact which extends to the first electrode and having a contact hole extending to the first source drain region; (f) forming an amorphous silicon layer within the link contact and in contact with the first electrode; (g) depositing a metal layer; and, (h) etching the metal layer to form a second electrode in contact with the amorphous silicon layer and electrically separated from the first electrode by the amorphous silicon layer, and to form a metal contact to the first source/drain region through the contact hole.
Claim 2
Independent Claim
217 words
A method for fabricating a programmable read only memory cell, the method comprising the steps of: (a) forming an implant region within a substrate; (b) forming a first conductive layer over the substrate; (c) selectively etching the first conductive layer to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for a transistor; (d) implanting atoms of a first conductivity type into the substrate into a first source/drain region on a first side of the gate region and into a second source/drain region on a second side of the gate region, wherein the second source/drain region is electrically coupled to the implant region; (e) forming an insulating layer over the first electrode, the insulating layer having a link contact which extends to the first electrode and having a contact hole extending to the first source drain region; (f) forming an amorphous silicon layer within the link contact and in contact with the first electrode; (g) depositing a metal layer; and, (h) etching the metal layer to form a second electrode in contact with the amorphous silicon layer and electrically separated from the first electrode by the amorphous silicon layer, and to form a metal contact to the first source/drain region through the contact hole.
Claim 3
Dependent Claim
15 words
A method as in claim 1 wherein step (b) the first conductive material comprises polysilicon.
Claim 4
Dependent Claim
21 words
A method as in claim 2 wherein in step (c) the first electrode also includes a metal-silicide formed over the polysilicon.
Claim 5
Dependent Claim
18 words
A method as in claim 1 wherein step (a) includes forming an n + region within a substrate.
Claim 6
Dependent Claim
31 words
A method as in claim 1 wherein step (f) includes the following substeps: (f.1) depositing amorphous silicon using low pressure chemical vapor deposition; and, (f.2) selectively etching the deposited amorphous silicon.
Claim 7
Independent Claim
168 words
A method for fabricating a fuse connected to a source/drain region of a transistor, the method comprising the steps of: (a) forming an implant region within a substrate; (b) forming a first conductive layer over the substrate; (c) selectively etching the first conductive layer to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for the transistor; (d) implanting atoms of a first conductivity type into the substrate into the source/drain region on a first side of the gate region, wherein the source/drain region is electrically coupled to the implant region; (e) forming an insulating layer over the first electrode, the insulating layer having a link contact which extends to the first electrode; (f) forming an amorphous silicon layer within the link contact and in contact with the first electrode; and, (g) forming a second electrode in contact with the amorphous silicon layer and electrically separated from the first electrode by the amorphous silicon layer.
Claim 8
Independent Claim
168 words
A method for fabricating a fuse connected to a source/drain region of a transistor, the method comprising the steps of: (a) forming an implant region within a substrate; (b) forming a first conductive layer over the substrate; (c) selectively etching the first conductive layer to form a first electrode on the substrate in physical and electrical contact with the implant region and to form a gate region for the transistor; (d) implanting atoms of a first conductivity type into the substrate into the source/drain region on a first side of the gate region, wherein the source/drain region is electrically coupled to the implant region; (e) forming an insulating layer over the first electrode, the insulating layer having a link contact which extends to the first electrode; (f) forming an amorphous silicon layer within the link contact and in contact with the first electrode; and, (g) forming a second electrode in contact with the amorphous silicon layer and electrically separated from the first electrode by the amorphous silicon layer.
Claim 9
Dependent Claim
18 words
A method as in claim 6 wherein step (a) includes forming an n + region within a substrate.
Claim 10
Dependent Claim
31 words
A method as in claim 6 wherein step (f) includes the following substeps: (f.1) depositing amorphous silicon using low pressure chemical vapor deposition; and, (f.2) selectively etching the deposited amorphous silicon.
Claim 11
Dependent Claim
15 words
A method as in claim 1 wherein in step (b) the first electrode comprises polysilicon.
Claim 12
Dependent Claim
16 words
A method as in claim 1 wherein in step (b) the first electrode comprises a metal-silicide.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |