Patent US6023075A successfully refreshed from Google Patents.
US6023075A
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US
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Electro-optical device and method for manufacturing the same
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1997-10-31
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Granted: 2000-02-08
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Expires: 2017-10-31
Abstract
Abstract An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips. The liquid crystal display device according to the present invention is characterized by that the peripheral circuits are not wholly fabricated into thin film transistors, but only those portions having a simple device structure, or those composed of a small number of devices, or those comprising an IC not easily available commercially, or those comprising an expensive integrated circuit, are fabricated by thin film transistors. According to the present invention, an electro-optical device is provided at an increased production yield with a reduced production cost.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:22
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13454; H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D86/00; H10D86/01; H10D86/021; H10D86/0221; H10D86/0223; H10D86/40; H10D86/441; H10D86/60; G02F1/13452; G02F1/136; G02F1/1362; G02F1/13624; G02F1/136245; G09; G09G; G09G2310/00; G09G2310/02; G09G2310/0264; G09G2310/0281
Claims Analysis
Total Claims: 60
Claim 1
Independent Claim
200 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V. sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 5 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 2
Dependent Claim
200 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V. sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 5 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 3
Dependent Claim
192 words
A semiconductor circuit having a pixel portion and a shift register, said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor. each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 4
Dependent Claim
192 words
A semiconductor circuit having a pixel portion and a shift register, said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor. each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 5
Dependent Claim
189 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 6
Dependent Claim
189 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 7
Dependent Claim
192 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 5 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 8
Dependent Claim
192 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 5 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 9
Dependent Claim
233 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 10
Dependent Claim
233 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 11
Dependent Claim
227 words
A semiconductor circuit having a pixel portion and a shift register said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and in the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 12
Dependent Claim
227 words
A semiconductor circuit having a pixel portion and a shift register said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and in the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 13
Dependent Claim
223 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially same the as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 14
Dependent Claim
223 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially same the as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 15
Dependent Claim
226 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 16
Dependent Claim
226 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, and wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 to control an absolute value of a threshold voltage of said n-channel thin film transistor to be substantially the same as an absolute value of a threshold voltage of said p-channel thin film transistor, wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less.
Claim 17
Dependent Claim
221 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said p-channel and n-channel thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 18
Dependent Claim
221 words
An active matrix display device having a pixel portion and a peripheral circuit portion, said peripheral portion including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film; a leveling film covering each of said p-channel and n-channel thin film transistors in both of the pixel portion and a part of the peripheral circuit portion, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 19
Dependent Claim
211 words
A semiconductor circuit having a pixel portion and a shift register said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 20
Dependent Claim
211 words
A semiconductor circuit having a pixel portion and a shift register said shift register including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the shift register, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 21
Dependent Claim
208 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 22
Dependent Claim
208 words
A semiconductor circuit having a pixel portion and an inverter said inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 23
Dependent Claim
211 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 24
Dependent Claim
211 words
A semiconductor circuit having a pixel portion and a clocked inverter said clocked inverter including at least one pair of complementary p-channel and n-channel thin film transistors, and said pixel portion including at least one thin film transistor, each of said transistors comprising: a crystalline semiconductor island on an insulating surface, said semiconductor island having source and drain regions and a channel region; a gate insulating film adjacent to at least said channel region; and a gate electrode adjacent to said gate insulating film, a leveling film covering each of said thin film transistors in both of the pixel portion and the clocked inverter, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 10 cm 2 /V.sec or more and said semiconductor island of n-channel thin film transistor has an electron mobility in the range of 15 cm 2 /V.sec or more, wherein at least one of said semiconductor islands comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said semiconductor islands has a thickness in the range of 5000 Å or less, wherein each of said semiconductor islands comprises oxygen at a concentration not higher than 7×10 19 cm -3 .
Claim 25
Dependent Claim
17 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said semiconductor is silicon.
Claim 26
Dependent Claim
22 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said gate electrode comprises crystalline silicon doped with phosphorus.
Claim 27
Dependent Claim
53 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said gate electrode is a multilayer film of crystalline silicon doped with phosphorus and a metal film thereon, said metal comprising at least a material selected from the group consisting of Mo, W, MoSi 2 , and WSi 2 .
Claim 28
Dependent Claim
29 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said semiconductor island comprises oxygen at a concentration not higher than 1×10 19 cm -3 .
Claim 29
Dependent Claim
32 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said crystalline semiconductor island exhibits a Raman peak shifted to a lower frequency side from 522 cm -1 .
Claim 30
Dependent Claim
27 words
A circuit according to claim 14 wherein said phosphorus doped in said crystalline silicon is at a concentration of 1×10 21 to 5×10 21 cm -3 .
Claim 31
Dependent Claim
39 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said source and drain regions of n-channel thin film transistor are introduced with phosphorus at a dose of 1×10 15 to 5×10 15 cm -3 .
Claim 32
Dependent Claim
22 words
A circuit according to any one of claims 2-4, 6-8, and 10-12 wherein said semiconductor island has a thickness of 500-5000 Å.
Claim 33
Dependent Claim
194 words
An active matrix display device including a pixel portion and a peripheral circuit portion comprising: a plurality of pixel electrodes formed on an insulating surface; a first plurality of thin film transistors being formed in the pixel portion on said insulating surface and being connected to said pixel electrodes; a second plurality of thin film transistors being formed in the peripheral circuit portion on said insulating surface, said second plurality of thin film transistors including at least one pair of complementary p-channel and n-channel thin film transistors; a leveling film covering both of the first and second plurality of thin film transistors in the pixel portion and a part of the peripheral circuit portion, wherein said second plurality of thin film transistors in said peripheral circuit include channel semiconductor layers having at least one of an electron mobility 15 cm 2 /V.s or more and a hole mobility of 10 cm 2 /V.s or more, wherein each of the channel semiconductor layers comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said channel semiconductor layers has a thickness of 5000 Å or less.
Claim 34
Dependent Claim
194 words
An active matrix display device including a pixel portion and a peripheral circuit portion comprising: a plurality of pixel electrodes formed on an insulating surface; a first plurality of thin film transistors being formed in the pixel portion on said insulating surface and being connected to said pixel electrodes; a second plurality of thin film transistors being formed in the peripheral circuit portion on said insulating surface, said second plurality of thin film transistors including at least one pair of complementary p-channel and n-channel thin film transistors; a leveling film covering both of the first and second plurality of thin film transistors in the pixel portion and a part of the peripheral circuit portion, wherein said second plurality of thin film transistors in said peripheral circuit include channel semiconductor layers having at least one of an electron mobility 15 cm 2 /V.s or more and a hole mobility of 10 cm 2 /V.s or more, wherein each of the channel semiconductor layers comprises boron at a concentration in the range of 1×10 15 to 1×10 18 cm -3 , wherein each of said channel semiconductor layers has a thickness of 5000 Å or less.
Claim 35
Dependent Claim
160 words
An active matrix display device including a pixel portion and a peripheral circuit portion comprising: a plurality of pixel electrodes formed on an insulating surface; a first plurality of thin film transistors being formed in the pixel portion on said insulating surface and being connected to said pixel electrodes; a second plurality of thin film transistors being formed in the peripheral portion on said insulating surface, said second plurality of thin film transistors including at least one pair of complementary p-channel and n-channel thin film transistors; a leveling film covering both of the first and second plurality of thin film transistors in the pixel portion and a part of the peripheral circuit portion, wherein said second thin film transistors in said peripheral circuit include channel semiconductor layers comprising silicon in which oxygen is contained at a concentration not higher than 7×10 19 cm -3 , wherein each of said channel semiconductor layers has a thickness of 5000 Å or less.
Claim 36
Dependent Claim
160 words
An active matrix display device including a pixel portion and a peripheral circuit portion comprising: a plurality of pixel electrodes formed on an insulating surface; a first plurality of thin film transistors being formed in the pixel portion on said insulating surface and being connected to said pixel electrodes; a second plurality of thin film transistors being formed in the peripheral portion on said insulating surface, said second plurality of thin film transistors including at least one pair of complementary p-channel and n-channel thin film transistors; a leveling film covering both of the first and second plurality of thin film transistors in the pixel portion and a part of the peripheral circuit portion, wherein said second thin film transistors in said peripheral circuit include channel semiconductor layers comprising silicon in which oxygen is contained at a concentration not higher than 7×10 19 cm -3 , wherein each of said channel semiconductor layers has a thickness of 5000 Å or less.
Claim 37
Dependent Claim
13 words
A device according to claim 21 or 22 wherein said semiconductor is silicon.
Claim 38
Dependent Claim
37 words
A device according to claim 21 or 22 wherein each of the first and second plurality of said thin film transistors comprises a gate electrode formed over said channel semiconductor layers having a gate insulating film therebetween.
Claim 39
Dependent Claim
16 words
A device according to claim 24 wherein said gate electrode comprises crystalline silicon doped with phosphorus.
Claim 40
Dependent Claim
47 words
A device according to claim 24 wherein said gate electrode is a multilayer film of crystalline silicon doped with phosphorus and a metal film thereon, said metal comprising at least a material selected from the group consisting of Mo, W, MoSi 2 , and WSi 2 .
Claim 41
Dependent Claim
29 words
A device according to claim 25 or 26 wherein said phosphorus doped in said crystalline silicon is at a concentration of 1×10 21 to 5×10 21 cm -3 .
Claim 42
Dependent Claim
28 words
A device according to claim 21 or 22 wherein said channel semiconductor layers exhibit a Raman peak shifted to a lower frequency side from 522 cm -1 .
Claim 43
Independent Claim
17 words
A device according to any one of claims 1, 5, and 9 wherein said semiconductor is silicon.
Claim 44
Independent Claim
22 words
A device according to any one of claims 1, 5, and 9 wherein said gate electrode comprises crystalline silicon doped with phosphorus.
Claim 45
Independent Claim
53 words
A device according to any one of claims 1, 5, and 9 wherein said gate electrode is a multilayer film of crystalline silicon doped with phosphorus and a metal film thereon, said metal comprising at least a material selected from the group consisting of Mo, W, MoSi 2 , and WSi 2 .
Claim 46
Independent Claim
29 words
A device according to any one of claims 1, 5, and 9 wherein said semiconductor island comprises oxygen at a concentration not higher than 1×10 19 cm -3 .
Claim 47
Independent Claim
32 words
A device according to any one of claims 1, 5, and 9 wherein said crystalline semiconductor island exhibits a Raman peak shifted to a lower frequency side from 522 cm -1 .
Claim 48
Dependent Claim
29 words
A device according to claim 30 or 31 wherein said phosphorus doped in said crystalline silicon is at a concentration of 1×10 21 to 5×10 21 cm -3 .
Claim 49
Independent Claim
39 words
A device according to any one of claims 1, 5, and 9 wherein said source and drain regions of n-channel thin film transistor are introduced with phosphorus at a dose of 1×10 5 to 5×10 5 cm -3 .
Claim 50
Independent Claim
22 words
A device according to any one of claims 1, 5, and 9 wherein said semiconductor island has a thickness of 500-5000 Å.
Claim 51
Dependent Claim
20 words
A circuit according to any one of claims 2-4, 6-8, and 10-12, wherein said leveling film comprises an organic resin.
Claim 52
Dependent Claim
15 words
A circuit according to claim 37, wherein said organic resin is a transparent polyimide resin.
Claim 53
Independent Claim
22 words
A device according to any one of claims 1, 5, 9, 21 and 22, wherein said leveling film comprises an organic resin.
Claim 54
Dependent Claim
15 words
A device according to claim 39, wherein said organic resin is a transparent polyimide resin.
Claim 55
Dependent Claim
58 words
A circuit according to any one of claims 2-4, 6-8, and 10-12, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 200 cm 2 /V.sec or less and said semiconductor island of n-channel thin film transistor has a electron mobility in the range of 300 cm 2 /V.sec or less.
Claim 56
Independent Claim
58 words
A device according to any one of claims 1, 5, and 9, wherein said semiconductor island of p-channel thin film transistor has a hole mobility in the range of 200 cm 2 /V.sec or less and said semiconductor island of n-channel thin film transistor has a electron mobility in the range of 300 cm 2 /V.sec or less.
Claim 57
Dependent Claim
47 words
A device according to claim 21, wherein said second plurality of thin film transistors in said peripheral circuit include channel semiconductor layers having at least one of an electron mobility 300 cm 2 /V.s or less and a hole mobility of 200 cm 2 /V.s or less.
Claim 58
Dependent Claim
34 words
A circuit according to any one of the claims 2-4, and 10-12, wherein said n-channel thin film transistor has an approximately same absolute value of a threshold voltage as said p-channel thin film transistor.
Claim 59
Independent Claim
34 words
A device according to any one of the claims 1, 5, 9, wherein said n-channel thin film transistor has an approximately same absolute value of a threshold voltage as said p-channel thin film transistor.
Claim 60
Dependent Claim
27 words
A circuit according to claim 15 wherein said phosphorus doped in said crystalline silicon is at a concentration of 1×10 21 to 5×10 21 cm -3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-02-07 | 2003-08-09 | 2004-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-02-07 | 2007-08-09 | 2008-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-02-07 | 2011-08-09 | 2012-02-08 | $7700.00 | Window Closed / Lapsed |