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Low temperature germanium-silicon on insulator thin-film transistor

Assignee: Leland Stanford Junior University
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Filing: 1991-03-01
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Granted: 1993-10-05
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Expires: 2011-03-01
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Abstract

Abstract MOS transistors are formed in thin films of Ge/Si alloys (Ge x Si 1-x ). According to the process of the present invention, polycrystalline films of Ge/Si are deposited using commercially-available LPCVD equipment, which in the preferred process uses silane and germane as the sources of Ge and Si. The deposited Ge x Si 1-x films are polycrystalline at temperatures for processing down to as below 400° C., and the films can be doped heavily by ion implantation and annealing at temperatures as low as 600° C. to give high mobility and dopant activation yielding very low resistivity. By carrying out the annealing step in the formation of the thin film transistors in the temperature range of 400° to 500° C., the films provide very large grain size, minimizing the impact of grain boundaries in the polycrystalline films where the thin film transistors are to be formed. As a result, thin film MOS transistors are fabricated at temperatures below 500° C., and as low as 400° C., by using Ge x Si 1-x deposition and doping technology. The resulting transistors have significantly improved electrical characteristics compared to thin film transistors fabricated in silicon films utilizing standard processing techniques.

Inventors

  • 👤 Krishna C. Saraswat
  • 👤 Tsu-Jae King

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 08:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 89 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said first layer comprising source, drain and channel regions is formed of a polycrystalline Ge x Si 1-x alloy, where 1>x>0, and wherein said transistor conductive gate is formed of a Ge y Si 1-y alloy, where 1>y>0.
Claim 2
Dependent Claim 89 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said first layer comprising source, drain and channel regions is formed of a polycrystalline Ge x Si 1-x alloy, where 1>x>0, and wherein said transistor conductive gate is formed of a Ge y Si 1-y alloy, where 1>y>0.
Claim 3
Dependent Claim 65 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, said conductive gate being formed of a polycrystalline Ge y Si 1-y alloy, where 1>y>0.
Claim 4
Dependent Claim 65 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, said conductive gate being formed of a polycrystalline Ge y Si 1-y alloy, where 1>y>0.
Claim 5
Dependent Claim 19 words
The MOS thin film transistor as claimed in claim 2 wherein the value of y is at least 0.25.
Claim 6
Dependent Claim 19 words
The MOS thin film transistor as claimed in claim 2 wherein the value of y is at least 0.5.
Claim 7
Dependent Claim 81 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said channel region is formed of a polycrystalline Ge x Si 1-x alloy wherein 1>x>0, said transistor conductive gate being formed of a Ge y Si 1-y alloy, where 1>y>0.
Claim 8
Dependent Claim 81 words
A MOS thin film transistor formed on an insulating substrate comprising a first layer of source and drain regions separated by a channel region, contacts to said source and drain region, a gate dielectric overlying said channel region, and a conductive gate overlying said gate dielectric and said channel region, wherein said channel region is formed of a polycrystalline Ge x Si 1-x alloy wherein 1>x>0, said transistor conductive gate being formed of a Ge y Si 1-y alloy, where 1>y>0.
Claim 9
Dependent Claim 19 words
The MOS thin film transistor as claimed in claim 5 wherein the value of y is at least 0.25.
Claim 10
Dependent Claim 19 words
The MOS thin film transistor as claimed in claim 5 wherein the value of y is at least 0.5.

References Cited (Backward Citations)

US3258663A Cited
US3890632A Cited
US4581620A Cited
US4502204A Cited
US4673957A Cited
US5057889A Cited
US5101247A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-10-04 1997-04-05 1997-10-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-10-04 2001-04-05 2001-10-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-10-04 2005-04-05 2005-10-05 $7700.00 Window Closed / Lapsed

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