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US4621276A
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Buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
Assignee: Texas Instruments Inc
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Filing: 1984-05-24
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Granted: 1986-11-04
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Expires: 2004-05-24
Abstract
Abstract The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.
Inventors
- 👤 Satwinder D. S. Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:20
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D86/00; H10D86/201; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
130 words
A semiconductor device which comprises: (a) an insulating base member, (b) spaced semiconductor material regions of opposite conductivity type disposed on said base an electrically isolated from each other, (c) one of an N and P channel MOS device formed in one of said regions, (d) the other of an N and P channel MOS device formed in the other of said regions, (e) one of said devices having a source region and a drain region, each of said source and drain regions having a section of P+ type an adjacent section of N+ type material, (f) connecting means electrically interconnected said N+ type and P+ type sections, (g) insulating means over said connecting means, and (h) a conductor layer over said insulating means and spaced from said connecting means.
Claim 2
Dependent Claim
130 words
A semiconductor device which comprises: (a) an insulating base member, (b) spaced semiconductor material regions of opposite conductivity type disposed on said base an electrically isolated from each other, (c) one of an N and P channel MOS device formed in one of said regions, (d) the other of an N and P channel MOS device formed in the other of said regions, (e) one of said devices having a source region and a drain region, each of said source and drain regions having a section of P+ type an adjacent section of N+ type material, (f) connecting means electrically interconnected said N+ type and P+ type sections, (g) insulating means over said connecting means, and (h) a conductor layer over said insulating means and spaced from said connecting means.
Claim 3
Dependent Claim
16 words
A semiccnductor device as set forth in claim 1 wherein said interconnecting means is a silicide.
Claim 4
Dependent Claim
26 words
A semiconductor device as set forth in claim 2 wherein said silicide is taken from the class consisting of tungsten silicide, titanium silicide and platinum silicide.
Claim 5
Dependent Claim
45 words
A semiconductor device as set forth in claim 1 wherein said MOS device defined in (e) is a P channel MOS device and wherein said P+ section is adjacent said channel and said N+ section abuts said P+ section and is remote from said channel.
Claim 6
Dependent Claim
45 words
A semiconductor device as set forth in claim 2 wherein said MOS device defined in (e) is a P channel MOS device and wherein said P+ section is adjacent said channel and said N+ section abuts said P+ section and is remote from said channel.
Claim 7
Dependent Claim
45 words
A semiconductor device as set forth in claim 3 wherein said MOS device defined in (e) is a P channel MOS device and wherein said P+ section is adjacent said channel and said N+ section abuts said P+ section and is remote from said channel.
Claim 8
Dependent Claim
23 words
A semiconductor device as set forth in claim 1 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
Claim 9
Dependent Claim
23 words
A semiconductor device as set forth in claim 2 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
Claim 10
Dependent Claim
23 words
A semiccnductor device as set forth in claim 3 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
Claim 11
Dependent Claim
23 words
A semiconductor device as set forth in claim 4 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
Claim 12
Dependent Claim
23 words
A semiconductor device as set forth in claim 5 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
Claim 13
Dependent Claim
23 words
A semiconductor device as set forth in claim 6 further including doped polycrystalline silicon interconnecting predetermined ones of said source and drain regions.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-11-03 | 1990-05-05 | 1990-11-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-11-03 | 1994-05-05 | 1994-11-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-11-03 | 1998-05-05 | 1998-11-04 | $7700.00 | Window Closed / Lapsed |