US5514879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate insulated field effect transistors and method of manufacturing the same
Assignee: Semiconductor Energy Laboratory Co Ltd
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Filing: 1995-06-07
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Granted: 1996-05-07
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Expires: 2015-06-07
Abstract
Abstract A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.
Inventors
- 👤 Shunpei Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:00
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0221; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D30/675; H10D30/6757; H10D86/40; H10D86/60; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/13624; G02F1/136245
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
112 words
A semiconductor field effect transistor comprising: a source semiconductor region containing a spoiling impurity; a drain semiconductor region containing said spoiling impurity; a channel semiconductor region containing said spoiling impurity and located adjacent to said source and drain regions; a gate electrode located adjacent to said channel region and insulated from said channel region through a gate insulating film; wherein the photo-sensitivities of said channel region and said source and drain regions are spoiled by said spoiling impurity and wherein the concentration of said spoiling impurity in said source and drain region near said channel region is greater than the concentration in said source and drain regions distant from said channel region.
Claim 2
Dependent Claim
112 words
A semiconductor field effect transistor comprising: a source semiconductor region containing a spoiling impurity; a drain semiconductor region containing said spoiling impurity; a channel semiconductor region containing said spoiling impurity and located adjacent to said source and drain regions; a gate electrode located adjacent to said channel region and insulated from said channel region through a gate insulating film; wherein the photo-sensitivities of said channel region and said source and drain regions are spoiled by said spoiling impurity and wherein the concentration of said spoiling impurity in said source and drain region near said channel region is greater than the concentration in said source and drain regions distant from said channel region.
Claim 3
Dependent Claim
32 words
The semiconductor field effect transistor of claim 1 wherein the concentration of said spoiling impurity in said channel semiconductor region is between 1×10 20 cm -3 and 8×10 21 cm -3 .
Claim 4
Dependent Claim
35 words
The semiconductor field effect transistor of claim 1 wherein the concentration of said spoiling impurity in said source and drain regions distant from said channel region is not higher than 7×10 19 cm -3 .
Claim 5
Dependent Claim
17 words
The semiconductor field effect transistor of claim 1 wherein said field effect transistor is a staggered type.
Claim 6
Dependent Claim
18 words
The semiconductor field effect transistor of claim 1 wherein said field effect transistor is an inverted staggered type.
Claim 7
Dependent Claim
25 words
The semiconductor field effect transistor of claim 1 wherein said spoiling impurity is an element selected from the group consisting of oxygen, carbon and nitrogen.
Claim 8
Dependent Claim
36 words
The semiconductor field effect transistor of claim 1 wherein the deviation of the drain current in said drain semiconductor region in an ON state due to an illumination of 2000 cd is not higher than 10%.
Claim 9
Dependent Claim
37 words
The semiconductor field effect transistor of claim 1 wherein the deviation of the drain current in said drain semiconductor region in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |