Gate insulated field effect transistors and method of manufacturing the same

Claim 2

A semiconductor field effect transistor comprising: a source electrode; a drain electrode; a source semiconductor region connected to said source electrode; a drain semiconductor region connected to said drain electrode; a channel semiconductor region electrically coupled with said source and drain electrodes only through said source and drain regions respectively and located between said source and drain regions; a gate electrode located just adjacent to said channel region and insulated from said channel region through a gate insulating film; a substrate having an insulating surface on which said source, drain, and channel regions and said gate electrode are formed; wherein the photo-sensitivities of (a) said channel region and (b) said source and drain regions are spoiled by selective introduction of a concentration of a spoiling impurity sufficient to substantially reduce the photosensitivity of said channel region with respect to the photosensitivities of said source and drain regions such that the concentration of said spoiling impurity in said source and drain regions is less than the concentration of said spoiling impurity in the channel region, and wherein the concentration of said spoiling impurity in said channel region is 1×10 20 cm -3 to 8×10 21 cm -3 and the concentration of the spoiling impurity in said source and drain regions is not higher than 7×10 19 cm -3 .

Claim 3

The semiconductor field effect transistor as claimed in claim 1 wherein said spoiling impurity is an element selected from the group consisting of oxygen, carbon, and nitrogen.

Claim 4

The semiconductor field effect transistor as claimed in claim 1 wherein drift of the drain current level passing through said channel region in the on-state of said transistor due to light incident thereupon is within 10%.

Claim 5

The semiconductor field effect transistor as claimed in claim 1 wherein drift of the drain current level passing through said channel region in the off-state of said transistor due to illumination is within two orders of magnitude.

Claim 6

The semiconductor field effect transistor as claimed in claim 1 wherein said substrate is transparent.

Claim 7

A semiconductor field effect transistor as in claim 1 where the source semiconductor region, the drain semiconductor region, and the channel semiconductor region are formed within one semiconductor layer.

Claim 8

A semiconductor field effect transistor as in claim 1 where the source and drain semiconductor regions both have either a p-type or an n-type conductivity.

Claim 9

The transistor of claim 1 wherein said transistor is a staggered type.

Claim 10

The transistor of claim 1 wherein said transistor is an inverted staggered type.

Claim 11

The semiconductor field effect transistor of claim 1 wherein the deviation of the drain current in said drain semiconductor region in an ON state due to an illumination of 2000 cd is not higher than 10%.

Claim 12

The semiconductor field effect transistor of claim 1 wherein the deviation of the drain current in said drain semiconductor region in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.

Claim 13

The semiconductor field effect transistor as claimed in claim 5 wherein said substrate is a glass substrate.

Claim 16

The system of claim 13 further comprising a display device operably connected to said plural field effect transistor system.

Claim 17

The system of claim 13 wherein said plurality of field effect transistors are staggered types.

Claim 18

The system of claim 13 wherein said plurality of field effect transistors are inverted staggered types.

Claim 19

The system of claim 13 wherein the deviation of the drain current in said drain semiconductor regions of said part of said field effect transistors in an ON state due to illumination of 2000 cd is not higher than 10%.

Claim 20

The system of claim 13 wherein the deviation of the drain current in said drain semiconductor regions of said part of said field effect transistors in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.

Claim 21

A semiconductor field effect transistor display operating device comprising: a substrate having an insulating surface and having a central area exposed to an incident light source and a peripheral area shielded from said incident light source; and a plurality of field effect transistors formed on the substrate, each comprising: a source semiconductor region; a drain semiconductor region; a channel semiconductor region electrically coupled with said source and drain regions and located therebetween; a gate electrode formed adjacent to said channel region and insulated from said channel region through a gate insulating film; wherein a photo-sensitivity of the channel regions of said field effect transistors in said central area is spoiled by selectively introducing a spoiling impurity into said channel regions at a concentration sufficient to substantially reduce said photo-sensitivity while any concentration of said spoiling impurity in said source, drain, and channel regions in said peripheral area is less than the concentration of said spoiling impurity in the channel regions in the central area.

Claim 22

A semiconductor field effect transistor display operating device comprising: a substrate having an insulating surface and having a central area exposed to an incident light source and a peripheral area shielded from said incident light source; and a plurality of field effect transistors formed on the substrate, each comprising: a source semiconductor region; a drain semiconductor region; a channel semiconductor region electrically coupled with said source and drain regions and located therebetween; a gate electrode formed adjacent to said channel region and insulated from said channel region through a gate insulating film; wherein a photo-sensitivity of the channel regions of said field effect transistors in said central area is spoiled by selectively introducing a spoiling impurity into said channel regions at a concentration sufficient to substantially reduce said photo-sensitivity while any concentration of said spoiling impurity in said source, drain, and channel regions in said peripheral area is less than the concentration of said spoiling impurity in the channel regions in the central area.

Claim 23

The device of claim 19 wherein the transistors in said central area are provided for supplying voltages to pixel electrodes of said display and the transistors in said peripheral area are provided for driving said transistors in said central area.

Claim 24

The device of claim 19 wherein said plurality of field effect transistors are staggered types.

Claim 25

The device of claim 19 wherein said plurality of field effect transistors are inverted staggered types.

Claim 26

A semiconductor field effect transistor comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, in which source, drain and channel regions are formed; and a gate electrode located adjacent to the channel region in said semiconductor layer with an insulating layer therebetween, wherein a spoiling impurity is added to a portion of said semiconductor layer in order to spoil photosensitivity of said portion, said portion including said channel region and a part of said source and drain regions close to said channel region while any concentration of said impurity in a part of said source and drain regions distant from said channel region is less than that of said impurity in said portion.

Claim 27

A semiconductor field effect transistor comprising: a substrate having an insulating surface; a semiconductor layer formed on said insulating surface, in which source, drain and channel regions are formed; and a gate electrode located adjacent to the channel region in said semiconductor layer with an insulating layer therebetween, wherein a spoiling impurity is added to a portion of said semiconductor layer in order to spoil photosensitivity of said portion, said portion including said channel region and a part of said source and drain regions close to said channel region while any concentration of said impurity in a part of said source and drain regions distant from said channel region is less than that of said impurity in said portion.

Claim 28

The transistor of claim 23 wherein said transistor is a staggered type.

Claim 29

The transistor of claim 23 wherein said transistor is an inverted staggered type.

Claim 30

The semiconductor field effect transistor of claim 23 wherein the deviation of the drain current in said drain region in an ON state due to an illumination of 2000 cd is not higher than 10%.

Claim 31

The semiconductor field effect transistor of claim 23 wherein the deviation of the drain current in said drain region in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.

Claim 32

An active matrix electro-optical device comprising: a substrate having an insulating surface having a display portion provided with a plurality of pixels and a peripheral circuit portion; a first plurality of transistors provided on the display portion of said substrate for switching said plurality of pixels; and a second plurality of transistors provided on the peripheral circuit portion of said substrate for driving said first plurality of transistors, wherein a concentration of an impurity selected from the group consisting of N, O and a combination thereof in a channel semiconductor region in each of said first plurality of transistors is higher than a concentration of said impurity in a channel semiconductor region in each of at least one of said second plurality of transistors.

Claim 33

An active matrix electro-optical device comprising: a substrate having an insulating surface having a display portion provided with a plurality of pixels and a peripheral circuit portion; a first plurality of transistors provided on the display portion of said substrate for switching said plurality of pixels; and a second plurality of transistors provided on the peripheral circuit portion of said substrate for driving said first plurality of transistors, wherein a concentration of an impurity selected from the group consisting of N, O and a combination thereof in a channel semiconductor region in each of said first plurality of transistors is higher than a concentration of said impurity in a channel semiconductor region in each of at least one of said second plurality of transistors.

Claim 34

The device of claim 28 wherein said first plurality of transistors and said second plurality of transistors are staggered types.

Claim 35

The device of claim 28 wherein said first plurality of transistors and said second plurality of transistors are inverted staggered types.

Claim 36

The active matrix electro-optical device of claim 28 wherein the deviation of drain current in said first plurality of transistors in an ON state due to an illumination of 2000 cd is not higher than 10%.

Claim 37

The active matrix electro-optical device of claim 28 wherein the deviation of drain current in said first plurality of transistors in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.

Claim 38

A semiconductor field effect transistor comprising: a source electrode; a drain electrode; a source semiconductor region containing a spoiling impurity connected to said source electrode; a drain semiconductor region containing a spoiling impurity connected to said drain electrode; a channel semiconductor region electrically coupled with said source and drain electrodes only through said source and drain regions respectively and located between said source and drain regions where the source semiconductor region, the drain semiconductor region, and the channel semiconductor region are formed within one semiconductor layer; a gate electrode located just adjacent to said channel semiconductor region and insulated from said channel semiconductor region through a gate insulating film; a substrate having an insulating surface on which said source, drain, and channel regions and said gate electrode are formed; wherein the photo-sensitivity of said channel semiconductor region is spoiled by introduction of a concentration of said spoiling impurity sufficient to substantially reduce the photosensitivity of said channel semiconductor region selectively into said channel semiconductor region such that any concentration of said spoiling impurity in said source and drain regions is less than the concentration of said spoiling impurity in the channel semiconductor region, and wherein the concentration of said spoiling impurity in said channel semiconductor region is 1×10 20 cm -3 to 8×10 21 cm -3 and the concentration of the spoiling impurity in said source and drain regions is not higher than 7×10 19 cm -3 .

Claim 39

A semiconductor field effect transistor comprising: a source electrode; a drain electrode; a source semiconductor region containing a spoiling impurity connected to said source electrode; a drain semiconductor region containing a spoiling impurity connected to said drain electrode; a channel semiconductor region electrically coupled with said source and drain electrodes only through said source and drain regions respectively and located between said source and drain regions where the source semiconductor region, the drain semiconductor region, and the channel semiconductor region are formed within one semiconductor layer; a gate electrode located just adjacent to said channel semiconductor region and insulated from said channel semiconductor region through a gate insulating film; a substrate having an insulating surface on which said source, drain, and channel regions and said gate electrode are formed; wherein the photo-sensitivity of said channel semiconductor region is spoiled by introduction of a concentration of said spoiling impurity sufficient to substantially reduce the photosensitivity of said channel semiconductor region selectively into said channel semiconductor region such that any concentration of said spoiling impurity in said source and drain regions is less than the concentration of said spoiling impurity in the channel semiconductor region, and wherein the concentration of said spoiling impurity in said channel semiconductor region is 1×10 20 cm -3 to 8×10 21 cm -3 and the concentration of the spoiling impurity in said source and drain regions is not higher than 7×10 19 cm -3 .

Claim 40

The semiconductor field effect transistor of claim 33 wherein the deviation of the drain current in said drain semiconductor region in an ON state due to an illumination of 2000 cd is not higher than 10%.

Claim 41

The semiconductor field effect transistor of claim 33 wherein the deviation of the drain current in said drain semiconductor region in an OFF state due to an illumination of 2000 cd is within two orders of magnitude.

Claim 42

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity wherein the concentration of said spoiling impurity is not higher than 7×10 19 cm -3 and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region and wherein the concentration of said impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said impurity in said intrinsic or substantially intrinsic region.

Claim 43

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity wherein the concentration of said spoiling impurity is not higher than 7×10 19 cm -3 and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region and wherein the concentration of said impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said impurity in said intrinsic or substantially intrinsic region.

Claim 44

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity between 1×10 20 cm -3 to 8×10 21 cm -3 sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region, and wherein the concentration of said spoiling impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said spoiling impurity in said intrinsic or substantially intrinsic region.

Claim 45

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity between 1×10 20 cm -3 to 8×10 21 cm -3 sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region, and wherein the concentration of said spoiling impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said spoiling impurity in said intrinsic or substantially intrinsic region.

Claim 50

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity between 1×10 20 cm -3 to 20 atom % sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region, and wherein the concentration of said spoiling impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said spoiling impurity in said intrinsic or substantially intrinsic region.

Claim 51

A semiconductor field effect transistor comprising: at least one of n-type or p-type semiconductor region containing a spoiling impurity and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region and insulated from said intrinsic or substantially intrinsic region through a gate insulating film; wherein the photosensitivity of said intrinsic or substantially intrinsic region is spoiled by selective introduction of a concentration of said impurity between 1×10 20 cm -3 to 20 atom % sufficient to substantially reduce the photosensitivity of said intrinsic or substantially intrinsic region, and wherein the concentration of said spoiling impurity in said at least one n-type or p-type semiconductor region is less than the concentration of said spoiling impurity in said intrinsic or substantially intrinsic region.

Claim 52

A semiconductor field effect transistor comprising: a substrate having an insulating surface; at least one n-type or p-type semiconductor region and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region with an insulating layer therebetween, wherein a photosensitivity spoiling impurity is added to said intrinsic or substantially intrinsic region and a portion of said at least one n-type or p-type semiconductor region close to said intrinsic or substantially intrinsic region while the concentration of said impurity in a part of said at least one n-type or p-type semiconductor region distant from said intrinsic or substantially intrinsic region is less than that of said impurity in said portion.

Claim 53

A semiconductor field effect transistor comprising: a substrate having an insulating surface; at least one n-type or p-type semiconductor region and an intrinsic or substantially intrinsic semiconductor region adjacent said n-type or p-type semiconductor region; a gate electrode located adjacent to said intrinsic or substantially intrinsic region with an insulating layer therebetween, wherein a photosensitivity spoiling impurity is added to said intrinsic or substantially intrinsic region and a portion of said at least one n-type or p-type semiconductor region close to said intrinsic or substantially intrinsic region while the concentration of said impurity in a part of said at least one n-type or p-type semiconductor region distant from said intrinsic or substantially intrinsic region is less than that of said impurity in said portion.