US7166509B2
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Write once read only memory with large work function floating gates
Assignee: Micron Technology Inc
•
Filing: 2004-09-02
•
Granted: 2007-01-23
•
Expires: 2024-09-02
Abstract
Abstract Structures and methods for write once read only memory employing floating gates are provided. The write once read only memory cell includes a floating gate transistor formed in a modified dynamic random access memory (DRAM) fabrication process. The floating gate transistor has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a large work function floating gate separated from the channel region by a gate insulator, and a control gate is separated from the floating gate by a gate dielectric. A plug is coupled to the first source/drain region and couples the first source/drain region to an array plate. A transmission line is coupled to the second source/drain region. The floating gate transistor can be programmed in two directions to trap charge in the high work function floating gate.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:12
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 44
Claim 1
Independent Claim
247 words
A method for operating a memory, comprising: programming one or more floating gate transistors in a DRAM array, wherein each floating gate transistor in the DRAM array includes a write once read only memory cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a gate insulator; wherein the floating gate is formed of a large work function material; a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; and a transmission line coupled to the second source/drain region; wherein programming the one or more floating gate transistors in the reverse direction includes: applying a first voltage potential to a first source/drain region of the floating gate transistor; applying a second voltage potential to a second source/drain region of the floating gate transistor; applying a gate potential to a control gate of the floating gate transistor; and wherein applying the first, second and control gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the high work function floating gate of the one or more floating gate transistors adjacent to the source region such that the one or more floating gate transistors become programmed floating gate transistors and operate at reduced drain source current in a forward direction.
Claim 2
Independent Claim
247 words
A method for operating a memory, comprising: programming one or more floating gate transistors in a DRAM array, wherein each floating gate transistor in the DRAM array includes a write once read only memory cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a gate insulator; wherein the floating gate is formed of a large work function material; a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; and a transmission line coupled to the second source/drain region; wherein programming the one or more floating gate transistors in the reverse direction includes: applying a first voltage potential to a first source/drain region of the floating gate transistor; applying a second voltage potential to a second source/drain region of the floating gate transistor; applying a gate potential to a control gate of the floating gate transistor; and wherein applying the first, second and control gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the high work function floating gate of the one or more floating gate transistors adjacent to the source region such that the one or more floating gate transistors become programmed floating gate transistors and operate at reduced drain source current in a forward direction.
Claim 3
Dependent Claim
33 words
The method of claim 1 , wherein applying a first voltage potential to the first source/drain region of the floating gate transistor includes grounding the first source/drain region of the floating gate transistor.
Claim 4
Dependent Claim
29 words
The method of claim 2 , wherein applying a second voltage potential to the second source/drain region includes applying a high voltage potential (VDD) to the second source/drain region.
Claim 5
Dependent Claim
33 words
The method of claim 1 , wherein applying a first voltage potential to the first source/drain region of the floating gate transistor includes applying a high voltage potential (VDD) to the array plate.
Claim 6
Dependent Claim
23 words
The method of claim 4 , wherein applying a second voltage potential to the second source/drain region includes grounding the second source/drain region.
Claim 7
Dependent Claim
49 words
The method of claim 1 , wherein applying a gate potential to the control gate of the floating gate transistor includes applying a gate potential to the control gate in order to create a conduction channel between the first and the second source/drain regions of the floating gate transistor.
Claim 8
Dependent Claim
77 words
The method of claim 1 , wherein the method further includes reading one or more floating gate transistors in the DRAM array by operating an addressed floating gate transistor in a forward direction, wherein operating the floating gate transistor in the forward direction includes: grounding the array plate; precharging the transmission line to a fractional voltage of VDD; and applying a control gate potential of approximately 1.0 Volt to the gate of the addressed floating gate transistor.
Claim 9
Dependent Claim
39 words
The method of claim 1 , wherein in creating a hot electron injection into the floating gate of the one or more floating gate transistors includes changing a threshold voltage for the floating gate transistor by approximately 0.5 Volts.
Claim 10
Independent Claim
245 words
A method for operating a write once read only memory, comprising: writing to one or more floating gate transistors in a DRAM array, wherein each floating gate transistor in the DRAM array includes a write once read only memory cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a gate insulator; wherein the floating gate is formed of a large work function material; a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; and a transmission line coupled to the second source/drain region; wherein writing to the one or more floating gate transistors includes writing to the one or more floating gate transistors in a first and a second direction, wherein writing in a first and a second direction includes: applying a first voltage potential to the first source/drain region of the floating gate transistor; applying a second voltage potential to the second source/drain region of the floating gate transistor; and applying a gate potential to the control gate of the floating gate transistor; and wherein applying the first, second and gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the large work function floating gate of the one or more floating gate transistors.
Claim 11
Independent Claim
245 words
A method for operating a write once read only memory, comprising: writing to one or more floating gate transistors in a DRAM array, wherein each floating gate transistor in the DRAM array includes a write once read only memory cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions; a floating gate separated from the channel region by a gate insulator; wherein the floating gate is formed of a large work function material; a control gate separated from the floating gate by a gate dielectric; a plug coupled to the first source/drain region, wherein the plug couples the first source/drain region to an array plate; and a transmission line coupled to the second source/drain region; wherein writing to the one or more floating gate transistors includes writing to the one or more floating gate transistors in a first and a second direction, wherein writing in a first and a second direction includes: applying a first voltage potential to the first source/drain region of the floating gate transistor; applying a second voltage potential to the second source/drain region of the floating gate transistor; and applying a gate potential to the control gate of the floating gate transistor; and wherein applying the first, second and gate potentials to the one or more floating gate transistors includes creating a hot electron injection into the large work function floating gate of the one or more floating gate transistors.
Claim 12
Dependent Claim
87 words
The method of claim 9 , wherein when writing in a first direction, applying a first voltage potential to the first source/drain region of the floating gate transistor includes grounding the first source/drain region of the floating gate transistor, applying a second voltage potential to the second source/drain region includes applying a high voltage potential (VDD) to the second source/drain region, and applying a gate potential to the control gate creates a conduction channel between the first and the second source/drain regions of the floating gate transistor.
Claim 13
Dependent Claim
77 words
The method of claim 9 , wherein the method further includes reading one or more floating gate transistors in the DRAM array by operating an addressed floating gate transistor in a forward direction, wherein operating the floating gate transistor in the forward direction includes: grounding the array plate; precharging the transmission line to a fractional voltage of VDD; and applying a control gate potential of approximately 1.0 Volt to the gate of the addressed floating gate transistor.
Claim 14
Dependent Claim
68 words
The method of claim 11 , wherein reading the one or more floating gate transistors includes using a sense amplifier to detect a change in an integrated drain current, and wherein when read the floating gate transistor will exhibit a change in an integrated drain current of approximately 12.5 μA when addressed over approximately 10 ns when no charge is programmed in the high work function floating gate.
Claim 15
Dependent Claim
58 words
The method of claim 12 , wherein the method further includes using the floating gate transistors in the DRAM array as active devices with gain, and wherein reading a programmed flash cell includes providing an amplification of the stored charge in the floating gate from 100 to 800,000 electrons over a read address period of approximately 10 ns.
Claim 16
Dependent Claim
87 words
The method of claim 9 , wherein when writing in a second direction, applying a first voltage potential to the first source/drain region of the floating gate transistor includes applying a high voltage potential (VDD) to the first source/drain region of the floating gate transistor, applying a second voltage potential to the second source/drain region includes grounding the second source/drain region, and applying a gate potential to the control gate creates a conduction channel between the first and the second source/drain regions of the floating gate transistor.
Claim 17
Dependent Claim
40 words
The method of claim 9 , wherein in creating a hot electron injection into the high work function floating gate of the addressed floating gate transistor includes changing a threshold voltage for the floating gate transistor by approximately 0.5 Volts.
Claim 18
Dependent Claim
48 words
The method of claim 9 , wherein in creating a hot electron injection into the high work function floating gate of the addressed floating gate transistor includes trapping a stored charge in the floating gate of the addressed floating gate transistor of approximately 10 12 electrons/cm 2 .
Claim 19
Dependent Claim
45 words
The method of claim 9 , wherein in creating a hot electron injection into the high work function floating gate of the addressed floating gate transistor includes trapping a stored charge in the floating gate of the addressed floating gate transistor of approximately 100 electrons.
Claim 20
Independent Claim
191 words
A method for forming a write once read only floating gate memory cell, comprising: forming a floating gate transistor in a modified dynamic random access memory (DRAM) fabrication process, wherein forming the floating gate transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a high work function floating gate above the gate insulator; forming a gate dielectric on the floating gate; and forming a control gate on the gate dielectric; forming an array plate; forming a conductive plug coupling the first source/drain region to the array plate; forming a transmission line coupled to the second source/drain region such that the write once read only floating gate memory cell can be programmed to have a trapped charge in the high work function floating gate by grounding the array plate, biasing the transmission line to a voltage higher than VDD, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.
Claim 21
Independent Claim
191 words
A method for forming a write once read only floating gate memory cell, comprising: forming a floating gate transistor in a modified dynamic random access memory (DRAM) fabrication process, wherein forming the floating gate transistor includes: forming a first source/drain region, a second source/drain region, and a channel region between the first and the second source/drain regions in a substrate; forming a gate insulator above the channel region; forming a high work function floating gate above the gate insulator; forming a gate dielectric on the floating gate; and forming a control gate on the gate dielectric; forming an array plate; forming a conductive plug coupling the first source/drain region to the array plate; forming a transmission line coupled to the second source/drain region such that the write once read only floating gate memory cell can be programmed to have a trapped charge in the high work function floating gate by grounding the array plate, biasing the transmission line to a voltage higher than VDD, and selecting the control gate by a wordline address, and wherein a programmed floating gate transistor will operate at reduced drain source current in a forward direction.
Claim 22
Dependent Claim
29 words
The method of claim 18 , wherein forming a gate insulator above the channel region includes forming a gate insulator having a thickness of at least 10 nanometers (nm).
Claim 23
Dependent Claim
36 words
The method of claim 18 , wherein forming a high work function floating gate includes forming the high work function floating gate of a refractory metal selected from the group of molybdenum (Mo) and tungsten (W).
Claim 24
Dependent Claim
57 words
The method of claim 18 , wherein forming a high work function floating gate includes forming the high work function floating gate of a large work function material selected from the group of p-type silicon germanium gates, p-type polycrystalline gate of silicon carbide, p-type polycrystalline gate of silicon oxycarbide, gallium nitride (GaN), and aluminum gallium nitride (AlGaN).
Claim 25
Dependent Claim
36 words
The method of claim 18 , wherein forming a high work function floating gate includes forming the high work function floating gate of a heavily doped p-type polysilicon with a vacuum work function of 5.3 eV.
Claim 26
Independent Claim
208 words
A method for operating a memory, comprising: programming one or more floating gate transistors, each floating gate transistor including; a semiconductor substrate having a first doping type, a first and a second diffused regions in the substrate having a second doping type opposite of the first doping type; a floating gate formed of high work function material separated from the substrate by a gate insulator layer and disposed between the first and second diffused regions; a control gate disposed above the floating gate and separated from the floating gate by a gate dielectric; and electrical contacts to the first and second diffused regions and the control gate; wherein programming the one or more floating gate transistors includes; applying a first potential to the electrical contacts to the first diffused region of the floating gate transistor; applying a second potential to the electrical contacts to the second diffused region of the floating gate transistor; applying a gate potential to the electrical contacts to the control gate; and wherein applying the first, second and gate potentials to the electrical contacts includes creating a hot electron injection into the floating gate formed of the high work function material such that the floating gate transistors operate at reduced drain to source current.
Claim 27
Independent Claim
208 words
A method for operating a memory, comprising: programming one or more floating gate transistors, each floating gate transistor including; a semiconductor substrate having a first doping type, a first and a second diffused regions in the substrate having a second doping type opposite of the first doping type; a floating gate formed of high work function material separated from the substrate by a gate insulator layer and disposed between the first and second diffused regions; a control gate disposed above the floating gate and separated from the floating gate by a gate dielectric; and electrical contacts to the first and second diffused regions and the control gate; wherein programming the one or more floating gate transistors includes; applying a first potential to the electrical contacts to the first diffused region of the floating gate transistor; applying a second potential to the electrical contacts to the second diffused region of the floating gate transistor; applying a gate potential to the electrical contacts to the control gate; and wherein applying the first, second and gate potentials to the electrical contacts includes creating a hot electron injection into the floating gate formed of the high work function material such that the floating gate transistors operate at reduced drain to source current.
Claim 28
Dependent Claim
27 words
The method for operating a memory of claim 23 further comprising the first potential including a ground potential and the second potential including a high potential (VDD).
Claim 29
Dependent Claim
27 words
The method for operating a memory of claim 23 further comprising the first potential including a high potential (VDD) and the second potential including a ground potential.
Claim 30
Dependent Claim
34 words
The method for operating a memory of claim 23 further comprising the one or more floating gate transistors including applying a gate potential to provide a current gain of the drain to source current.
Claim 31
Dependent Claim
26 words
The method for operating a memory of claim 23 further comprising the high work function material including materials having a vacuum work function of 5.3 eV.
Claim 32
Dependent Claim
51 words
The method for operating a memory of claim 23 further comprising the high work function material including one or more materials selected from the list consisting of molybdenum (Mo), tungsten (W), silicon germanium (SiGe), silicon carbide (SiC), silicon oxycarbide (SiOC), aluminum gallium nitride (AlGaN), gallium nitride (GaN) and p type polysilicon.
Claim 33
Dependent Claim
24 words
The method for operating a memory of claim 23 further comprising programming the one or more floating gate transistors includes programming in both directions.
Claim 34
Dependent Claim
19 words
The method for operating a memory of claim 23 further comprising erasing the one or more floating gate transistors.
Claim 35
Dependent Claim
21 words
The method for operating a memory of claim 30 further comprising erasing by applying a negative potential to the control gate.
Claim 36
Dependent Claim
28 words
The method for operating a memory of claim 23 further comprising a number of hot electrons injected into the floating gate greater than 10 12 electrons/cm 2 .
Claim 37
Dependent Claim
22 words
The method for operating a memory of claim 23 further comprising the gate insulator layer having a thickness greater than 10 nanometers.
Claim 38
Independent Claim
153 words
A method for forming a floating gate memory cell, comprising: forming at least one floating gate transistor, wherein forming each one of the at least one floating gate transistor includes: forming a first and a second diffused regions in a semiconductor substrate having a first doping type, the first and second diffused regions having a second doping type opposite of the first doping type; forming a floating gate of a high work function material separated from the substrate by a gate insulator layer and disposed between the first and second diffused regions; forming a control gate disposed above the floating gate and separated from the floating gate by a gate dielectric; and forming electrical contacts to the first and second diffused regions and the control gate; and connecting the electrical contacts such that the floating gate memory can be programmed to have a trapped charge in the high work function material floating gate.
Claim 39
Independent Claim
153 words
A method for forming a floating gate memory cell, comprising: forming at least one floating gate transistor, wherein forming each one of the at least one floating gate transistor includes: forming a first and a second diffused regions in a semiconductor substrate having a first doping type, the first and second diffused regions having a second doping type opposite of the first doping type; forming a floating gate of a high work function material separated from the substrate by a gate insulator layer and disposed between the first and second diffused regions; forming a control gate disposed above the floating gate and separated from the floating gate by a gate dielectric; and forming electrical contacts to the first and second diffused regions and the control gate; and connecting the electrical contacts such that the floating gate memory can be programmed to have a trapped charge in the high work function material floating gate.
Claim 40
Dependent Claim
25 words
The method for forming a floating gate memory cell of claim 34 further comprising the gate insulator layer having a thickness greater than 10 nanometers.
Claim 41
Dependent Claim
31 words
The method for forming a floating gate memory cell of claim 34 further comprising a number of hot electrons injected into the floating gate greater than 10 12 electrons/cm 2 .
Claim 42
Dependent Claim
33 words
The method for forming a floating gate memory cell of claim 34 further comprising erasing the trapped charge in the high work function material by applying a negative potential to the control gate.
Claim 43
Dependent Claim
54 words
The method for forming a floating gate memory cell of claim 34 further comprising the high work function material including one or more materials selected from the list consisting of molybdenum (Mo), tungsten (W), silicon germanium (SiGe), silicon carbide (SiC), silicon oxycarbide (SiOC), aluminum gallium nitride (AlGaN), gallium nitride (GaN) and p type polysilicon.
Claim 44
Dependent Claim
29 words
The method for forming a floating gate memory cell of claim 34 further comprising the high work function material including materials having a vacuum work function of 5.3 eV.
References Cited (Backward Citations)
US3665423A
Cited
US3641516A
Cited
US3877054A
Cited
US3964085A
Cited
US4152627A
Cited
US4217601A
Cited
US4413022A
Cited
US4507673A
Cited
US4333808A
Cited
US4939559A
Cited
US4661833A
Cited
US4920071A
Cited
JPS62199019A
Cited
US5021999A
Cited
US5293560A
Cited
US5006192A
Cited
US4888733A
Cited
US5042011A
Cited
US5111430A
Cited
US5027171A
Cited
JPH03222367A
Cited
US6110529A
Cited
US5840897A
Cited
US5253196A
Cited
US5449941A
Cited
US5303182A
Cited
US5399516A
Cited
US5388069A
Cited
US5280205A
Cited
US5317535A
Cited
US5550770A
Cited
JPH06224431A
Cited
US5438544A
Cited
JPH06302828A
Cited
US5539279A
Cited
US6521950B1
Cited
US5493140A
Cited
US5298447A
Cited
US5467306A
Cited
US5430670A
Cited
US5424993A
Cited
US5541872A
Cited
US5541871A
Cited
US5434815A
Cited
US5508543A
Cited
US5410504A
Cited
US5485422A
Cited
US5457649A
Cited
US5572459A
Cited
US5602777A
Cited
US5627781A
Cited
US5600587A
Cited
US5477485A
Cited
US6714455B2
Cited
US6353554B1
Cited
JPH08255878A
Cited
US5530668A
Cited
US5595606A
Cited
US5530581A
Cited
US5801105A
Cited
US5714766A
Cited
US5627785A
Cited
US5735960A
Cited
US6387712B1
Cited
US5768192A
Cited
US5912488A
Cited
US6059885A
Cited
US5801401A
Cited
US6166401A
Cited
US5959896A
Cited
US5740104A
Cited
US5754477A
Cited
US5989958A
Cited
US5852306A
Cited
US5856688A
Cited
US6115281A
Cited
US6143636A
Cited
US6238976B1
Cited
US6072209A
Cited
US5936274A
Cited
US5973356A
Cited
US6150687A
Cited
US6013553A
Cited
US6031263A
Cited
US6249020B1
Cited
US5886368A
Cited
US6552387B1
Cited
US6566699B2
Cited
US6020024A
Cited
US6281144B1
Cited
US6161500A
Cited
US6313518B1
Cited
US5828605A
Cited
US6194228B1
Cited
US6140181A
Cited
US6351411B2
Cited
US6545314B2
Cited
US6232643B1
Cited
US6246606B1
Cited
US6252793B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2010-01-22 | 2010-07-24 | 2011-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2014-01-22 | 2014-07-24 | 2015-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2018-01-22 | 2018-07-24 | 2019-01-23 | $7700.00 | Window Closed / Lapsed |