Patent US6483736B2 successfully refreshed from Google Patents.
US6483736B2
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Vertically stacked field programmable nonvolatile memory and method of fabrication
Assignee: SanDisk Technologies LLC
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Filing: 2001-08-24
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Granted: 2002-11-19
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Expires: 2021-08-24
Abstract
Abstract A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
Inventors
- 👤 Mark G. Johnson
- 👤 Thomas H. Lee
- 👤 Vivek Subramanian
- 👤 Paul Michael Farmwald
- 👤 James M. Cleeves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:44
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/06; G11C11/00; G11C11/56; G11C11/5692; G11C13/00; G11C13/0002; G11C13/0021; G11C13/003; G11C17/14; G11C17/16; G11C17/165; H; H10; H10B; H10B63/00; H10B63/80; H10B63/84; H10N; H10N70/00; H10N70/011; H10N70/801; H10N70/821; H10N70/826; G11C2213/00; G11C2213/70; G11C2213/71; G11C2213/76
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
33 words
A 3-dimensional memory array built above a substrate, the memory array comprising: N layers of memory cells; N+1 layers of conductors; said memory cells and conductors fabricated using no more than N+1 masks.
Claim 2
Dependent Claim
33 words
A 3-dimensional memory array built above a substrate, the memory array comprising: N layers of memory cells; N+1 layers of conductors; said memory cells and conductors fabricated using no more than N+1 masks.
Claim 3
Dependent Claim
23 words
A memory comprising: the memory array of claim 1 ; and at least one contact which electrically couples said conductors to the substrate.
Claim 4
Dependent Claim
19 words
The memory array of claim 1 wherein each memory cell comprises a state change element and a steering element.
Claim 5
Dependent Claim
45 words
The memory array of claim 1 wherein the layers of conductors are disposed between memory cell layers and are arranged such that a vertical projection of a first conductor in a first layer of conductors intersects a second conductor in a second layer of conductors.
Claim 6
Dependent Claim
20 words
The memory array of claim 4 wherein the conductors run in substantially orthogonal directions between sequential layers of memory cells.
Claim 7
Dependent Claim
11 words
The memory of claim 2 wherein the substrate comprises monocrystalline silicon.
Claim 8
Dependent Claim
18 words
The memory array of claims 1 , 3 , 4 or 5 wherein the substrate comprises monocrystalline silicon.
Claim 9
Dependent Claim
18 words
The memory of claim 1 wherein each level of conductors is shared between 2 layers of memory cells.
Claim 10
Dependent Claim
11 words
The memory of claim 8 wherein the substrate comprises monocrystalline silicon.
Claim 11
Dependent Claim
18 words
The memory of claim 9 wherein at least some conductors are self-aligned with at least some memory cells.
Claim 12
Dependent Claim
47 words
A 3-dimensional memory built above a substrate, the memory comprising: N layers of memory cells; N+1 layers of conductors; at least one contact connecting each of the layers of conductors to the substrate; said memory cells, conductors and contacts being fabricated with no more than 2N+1 masks.
Claim 13
Dependent Claim
47 words
A 3-dimensional memory built above a substrate, the memory comprising: N layers of memory cells; N+1 layers of conductors; at least one contact connecting each of the layers of conductors to the substrate; said memory cells, conductors and contacts being fabricated with no more than 2N+1 masks.
Claim 14
Dependent Claim
16 words
The memory of claim 11 wherein the memory is fabricated with no more than N+2 masks.
Claim 15
Dependent Claim
13 words
The memory of claims 11 or 12 wherein the substrate comprises monocrystalline silicon.
Claim 16
Dependent Claim
20 words
The memory of claims 11 or 12 wherein at least some conductors are self-aligned with at least some memory cells.
Claim 17
Dependent Claim
20 words
The memory of claims 11 or 12 wherein at least some conductors are shared between successive layers of memory cells.
Claim 18
Dependent Claim
33 words
The memory array of claim 11 or 12 wherein the conductors are disposed between memory cell layers and are arranged such that a vertical projection of a first conductor intersects a second conductor.
Claim 19
Dependent Claim
22 words
The memory array of claim 11 or 12 wherein between sequential layers of memory cells the conductors run in substantially orthogonal directions.
Claim 20
Dependent Claim
19 words
The memory array of claim 1 wherein each memory cell comprises a state change element and a steering element.
Claim 21
Dependent Claim
84 words
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising: N layers of memory cells, each memory cell comprising a state change element and a steering element; N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer; at least one contact connecting each conductor to the substrate; said memory cells, conductors and contacts being fabricated with no more than 2N+1masks.
Claim 22
Dependent Claim
84 words
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising: N layers of memory cells, each memory cell comprising a state change element and a steering element; N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer; at least one contact connecting each conductor to the substrate; said memory cells, conductors and contacts being fabricated with no more than 2N+1masks.
Claim 23
Dependent Claim
100 words
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising: N layers of memory cells, each memory cell comprising a state change element and a steering element; N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer, and a memory cell is formed between said first and second conductors at the projection; at least one contact connecting each conductor to the substrate; said memory cells, conductors and contacts being fabricated with no more than N+2 masks.
Claim 24
Dependent Claim
100 words
A 3-dimensional memory built above a monocrystalline substrate, the memory comprising: N layers of memory cells, each memory cell comprising a state change element and a steering element; N+1 layers of conductors shared between successive memory cell layers and arranged such that a vertical projection of a first conductor in a first layer intersects a second conductor in a second layer, and a memory cell is formed between said first and second conductors at the projection; at least one contact connecting each conductor to the substrate; said memory cells, conductors and contacts being fabricated with no more than N+2 masks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-18 | 2006-05-20 | 2006-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-18 | 2010-05-20 | 2010-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-18 | 2014-05-20 | 2014-11-19 | $7700.00 | Window Closed / Lapsed |