US5654220A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a stacked 3D integrated circuit structure
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-06-07
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Granted: 1997-08-05
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Expires: 2015-06-07
Abstract
Abstract General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Inventors
- 👤 Glenn Joseph Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:42
CPC Classifications
H; H10; H10W; H10W90/00; H10P; H10P95/00; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/011; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/688; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/136; G02F1/1362; G02F1/136277; G02F1/136281; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10D89/00; H10D89/10; H10W70/682; H10W72/00; H10W72/20; H10W72/221; H10W72/29; H10W72/90; H10W72/941; H10W72/942; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928; Y10S438/938; Y10S438/942; Y10S438/967; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/49155; Y10T29/49162; Y10T29/49165; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4921
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
63 words
A method of making a stacked integrated circuit structure comprising the steps of: forming first and second flexible membranes each including a plurality of electrically interconnected semiconductor devices; bonding a principal surface of the first flexible membrane to the second flexible membrane; and interconnecting at least one semiconductor device in the first flexible membrane to a semiconductor device in the second flexible membrane.
Claim 2
Independent Claim
63 words
A method of making a stacked integrated circuit structure comprising the steps of: forming first and second flexible membranes each including a plurality of electrically interconnected semiconductor devices; bonding a principal surface of the first flexible membrane to the second flexible membrane; and interconnecting at least one semiconductor device in the first flexible membrane to a semiconductor device in the second flexible membrane.
Claim 3
Dependent Claim
31 words
The method of claim 1, further including the step, prior to bonding, of aligning the first and second flexible membranes by observing optical alignment marks on one of the flexible membranes.
Claim 4
Dependent Claim
67 words
The method of claim 1 wherein at least some of the semiconductor devices are optical devices, and the step of interconnecting includes the steps of: forming vias in each flexible membrane, the vias each being associated with one of the optical devices; and aligning the vias in the first flexible membrane with the vias in the second flexible membrane, thereby forming waveguides for connecting the optical devices.
Claim 5
Independent Claim
150 words
A method of forming an interconnect structure for a circuit membrane, comprising the steps of: providing a semiconductor film; forming a flexible dielectric membrane on a principal surface of the semiconductor film; forming a layer of amorphous silicon on the membrane; patterning the amorphous silicon layer to form trenches and vias therein; depositing a layer of metal over the patterned amorphous silicon; patterning the deposited layer of metal, thereby forming metal traces; forming a second layer of amorphous silicon overlying the traces; patterning the second layer of amorphous silicon; forming a second dielectric layer over the second patterned layer of amorphous silicon; forming etch vias penetrating the dielectric layer to the underlying second layer of amorphous silicon; and removing the first and second layers of amorphous silicon through the etch vias, thereby leaving the metal traces supported at the vias by the dielectric membrane and overlain by the dielectric layer.
Claim 6
Independent Claim
150 words
A method of forming an interconnect structure for a circuit membrane, comprising the steps of: providing a semiconductor film; forming a flexible dielectric membrane on a principal surface of the semiconductor film; forming a layer of amorphous silicon on the membrane; patterning the amorphous silicon layer to form trenches and vias therein; depositing a layer of metal over the patterned amorphous silicon; patterning the deposited layer of metal, thereby forming metal traces; forming a second layer of amorphous silicon overlying the traces; patterning the second layer of amorphous silicon; forming a second dielectric layer over the second patterned layer of amorphous silicon; forming etch vias penetrating the dielectric layer to the underlying second layer of amorphous silicon; and removing the first and second layers of amorphous silicon through the etch vias, thereby leaving the metal traces supported at the vias by the dielectric membrane and overlain by the dielectric layer.
Claim 7
Dependent Claim
30 words
The method of claim 4, further comprising the steps of: forming additional metal traces supported on the dielectric layer; and forming an additional dielectric layer overlying the additional metal traces.
Claim 8
Dependent Claim
31 words
The method of claim 4, further comprising, after the step of forming the second layer of amorphous silicon, of depositing a layer of metal on the second layer of amorphous silicon.
References Cited (Backward Citations)
US4070230A
Cited
US4131985A
Cited
US4618397A
Cited
US4702336A
Cited
US4952446A
Cited
US4721938A
Cited
US5110373A
Cited
US4957882A
Cited
US4857481A
Cited
US5071510A
Cited
US5203731A
Cited
US5358909A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |