Stacked semiconductor memory

Claim 2

A semiconductor memory having a plurality of memory cells (M) for electrically storing data, characterized in that said plurality of memory cells (M) are arranged in a three-dimensional matrix, the three-dimensional memory cell structure is formed of a plurality of planar memory cell arrays (12) aligned and stacked with a plurality of memory cells (M) arranged in a matrix shape in a direction substantially perpendicularly to the planar memory cell arrays; and that said semiconductor memory comprises a plurality of first wiring means (w) for commonly connecting each of a plurality of first planar memory cell arrays substantially parallel with each other, memory cells (M) included in each of the first planar'memory cell arrays being connecting commonly to one of said first wiring means (w), and a plurality of second wiring means (B) for respectively commonly connecting a plurality of linear memory cell arrays which are included in a plurality of second planar memory cell arrays substantially orthogonally intersecting the first planar memory cell arrays and which substantially orthogonally intersect the first planar memory cell arrays, said linear memory cell arrays extending substantially parallel to each other and each of the linear memory cell arrays included in the second planar memory cell arrays being connected commonly to one of said second wiring means (B).

Claim 3

A semiconductor memory according to claim 1, characterized in that each of said first wiring means comprises a plurality of third wiring means (w) for respectively commonly connecting memory cell groups included in a plurality of second linear memory cell arrays arranged substantially in a direction perpendicularly extending to said second planar memory cell arrays in the memory cells included in each of said first planar memory cell arrays (12), said third wiring means (w) being electrically conducted with each other.

Claim 4

A semiconductor memory according to claim 2, characterized in that said plurality of third wiring means (w) extend in parallel with each other and substantially in parallel with said first planar memory cell arrays.

Claim 5

A semiconductor memory according to claim 3, characterized in that said first wiring means further comprises fourth wiring means (W) for electrically connecting said third wiring means (w) each connected to the second linear memory cell arrays included in said each of the first planar memory cell arrays (12) at the position corresponding to substantially externally of said memory cell structure.

Claim 6

A semiconductor memory according to claim 4, characterized in that said fourth wiring means (W) are provided corresponding to said plurality of the first planar memory cell arrays.

Claim 7

A semiconductor memory according to claim 4, characterized in that said first planar memory cell arrays are each formed on a plurality of layers (10) electrically isolated from each other, said layers are sequentially stacked to have a laminar structure.

Claim 8

A semiconductor memory according to claim 4, characterized in that said first planar memory cell arrays are formed to substantially orthogonally intersect a plurality of layers (10) electrically isolated from each other, said layers are sequentially stacked to form a laminar structure.

Claim 9

A semiconductor memory according to claim 6, characterized in that said plurality of second wiring means (B) extends to substantially orthogonally intersect said layers (10) for commonly connecting said plurality of first linear memory cell arrays included in said second planar memory cell arrays.

Claim 10

A semiconductor memory system comprising a semiconductor memory and decoder means (20) for receiving an address input signal and for activating desired memory cells of said semiconductor memory, characterized in that said semiconductor memory comprises a plurality of layers (10) electrically isolated from each other and sequentially stacked to form a laminar structure, a plurality of cell matrix structures (12) having a plurality of memory cells aligned in row and column directions on the surfaces of said layers, a plurality of bit lines (B) for commonly connecting a plurality of the first linear memory cell arrays respectively formed of memory cells arranged in the same column direction of the memory cells included in the cell matrix structure on each of said layers, and a plurality of word lines for commonly connecting a plurality of second linear memory cell arrays formed of memory cells arranged in the same row direction of the memory cells included in the memory cell matrix structure on each of said layers and substantially orthogonally intersecting the first linear memory cell arrays, and that said decoder means (20) is electrically connected through said word lines (w) to said semiconductor memory, stacked correspondingly to laminar units formed respectively of said plurality of second linear memory cell arrays stacked via said layers and formed by arranging in parallel with each other a plurality of linear decoder element arrays respectively formed of a plurality of stacked decoder elements (22) including active elements (24, 24', 26, 26'), each of said linear decoder element arrays including wiring means (L2) for commonly connecting said plurality of word lines (w31, w 32 , w 33 , 34) which respectively connect a plurality of second linear memory cell arrays stacked with each other and included in each of said laminar units corresponding to the linear decoder element array and for connecting between predetermined said active elements (24, 26) provided therein. said wiring means (L2) extending to substantially crthogonally intersect said layers (12).

Claim 11

A semiconductor memory system comprising a semiconductor memory and decoder means (20) for receiving an address input signal and for activating desired memory cells of said semiconductor memory, characterized in that said semiconductor memory comprises a plurality of layers (10) electrically isolated from each other and sequentially stacked to form a laminar structure, a plurality of cell matrix structures (12) having a plurality of memory cells aligned in row and column directions on the surfaces of said layers, a plurality of bit lines (B) for commonly connecting a plurality of the first linear memory cell arrays respectively formed of memory cells arranged in the same column direction of the memory cells included in the cell matrix structure on each of said layers, and a plurality of word lines for commonly connecting a plurality of second linear memory cell arrays formed of memory cells arranged in the same row direction of the memory cells included in the memory cell matrix structure on each of said layers and substantially orthogonally intersecting the first linear memory cell arrays, and that said decoder means (20) is electrically connected through said word lines (w) to said semiconductor memory, stacked correspondingly to laminar units formed respectively of said plurality of second linear memory cell arrays stacked via said layers and formed by arranging in parallel with each other a plurality of linear decoder element arrays respectively formed of a plurality of stacked decoder elements (22) including active elements (24, 24', 26, 26'), each of said linear decoder element arrays including wiring means (L2) for commonly connecting said plurality of word lines (w31, w 32 , w 33 , 34) which respectively connect a plurality of second linear memory cell arrays stacked with each other and included in each of said laminar units corresponding to the linear decoder element array and for connecting between predetermined said active elements (24, 26) provided therein. said wiring means (L2) extending to substantially crthogonally intersect said layers (12).