Vertically formed semiconductor random access memory device

Claim 2

A semiconductor memory device comprising: a substrate having a surface; a first transistor at least partially overlying the surface of the substrate, the first transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region; a second transistor overlying the first transistor, the second transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region; and electrical interconnects coupled to both the first transistor and the second transistor to connect the first and second transistors in series between a first node and a second node of said semiconductor memory device.

Claim 3

The semiconductor memory device of claim 1 further comprising: a third transistor formed at least partially overlying the surface of the substrate, the third transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region; a fourth transistor overlying the third transistor, the fourth transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region; and electrical interconnect material coupling the third transistor and the fourth transistor to one of either the first transistor or the second transistor.

Claim 4

The semiconductor memory device of claim 2 wherein the third and fourth transistors are both formed as N-channel transistors.

Claim 5

The semiconductor memory device of claim 1 wherein both the first and second transistors are formed as N-channel transistors.

Claim 6

The semiconductor memory device of claim 1 wherein the substrate further comprises: a diffusion region within the substrate, the diffusion region underlying the first transistor.

Claim 7

The semiconductor memory device of claim 5 wherein the diffusion region further comprises: a silicided region adjacent the diffusion region.

Claim 8

The semiconductor memory device of claim 1 wherein the first transistor is coupled to a resistive device via a conductive interconnection.

Claim 9

The semiconductor memory device of claim 7 wherein the resistive device is a resistor.

Claim 10

The semiconductor memory device of claim 7 wherein the resistive device is a P-channel transistor.

Claim 11

The semiconductor memory device of claim 7 wherein a capacitive element is adjacent said conductive interconnection.

Claim 12

The semiconductor memory device of claim 7 wherein the conductive interconnection directly underlies said resistive device.

Claim 13

The semiconductor memory device of claim 1 wherein one of either the first transistor or the second transistor has a composite gate dielectric having a first region made of a first dielectric material and a second region made of a second dielectric material.

Claim 14

A semiconductor memory device comprising: a substrate having a surface; a first vertical structure at least partially overlying the surface of the substrate, the first vertical structure having a first vertical transistor underlying a first semiconductor device; a second vertical structure at least partially overlying the surface of the substrate and laterally adjacent the first vertical structure, the second vertical structure having a second vertical transistor underlying a second semiconductor device; and electrical interconnects used to: (1) couple the first vertical transistor in series with the first semiconductor device; (2) couple the second vertical transistor in series with the second semiconductor device; and (3) couple the first vertical structure to the second vertical structure.

Claim 15

A semiconductor memory device comprising: a substrate having a surface; a first vertical structure at least partially overlying the surface of the substrate, the first vertical structure having a first vertical transistor underlying a first semiconductor device; a second vertical structure at least partially overlying the surface of the substrate and laterally adjacent the first vertical structure, the second vertical structure having a second vertical transistor underlying a second semiconductor device; and electrical interconnects used to: (1) couple the first vertical transistor in series with the first semiconductor device; (2) couple the second vertical transistor in series with the second semiconductor device; and (3) couple the first vertical structure to the second vertical structure.

Claim 16

The semiconductor memory device of claim 13 wherein the first and second semiconductor devices are respectively third and fourth vertical transistors.

Claim 17

The semiconductor memory device of claim 13 wherein the first and second vertical transistors each have a first current electrode, a second current electrode overlying the first current electrode, a channel region between the first and second current electrodes, and at least one gate electrode adjacent the channel region.

Claim 18

The semiconductor memory device of claim 13 wherein both the first and second transistors are formed as N-channel transistors.

Claim 19

The semiconductor memory device of claim 13 wherein the substrate further comprises: a diffusion region within the substrate, the diffusion region underlying the first transistor.

Claim 20

The semiconductor memory device of claim 13 wherein the diffusion region further comprises: a silicided region adjacent the diffusion region.

Claim 21

The semiconductor memory device of claim 13 wherein the first transistor is coupled to a resistive device via a conductive interconnection.

Claim 22

The semiconductor memory device of claim 19 wherein the resistive device is a resistor.

Claim 23

The semiconductor memory device of claim 19 wherein the resistive device is a P-channel transistor.

Claim 24

The semiconductor memory device of claim 19 wherein a capacitive element is adjacent said conductive interconnection.

Claim 25

The semiconductor memory device of claim 19 wherein the conductive interconnection directly underlies said resistive device.

Claim 26

The semiconductor memory device of claim 13 wherein one of either the first transistor or the second transistor has a composite gate dielectric having a first region made of a first dielectric material and a second region made of a second dielectric material.

Claim 27

A semiconductor random access memory device comprising: a substrate; a first vertical transistor formed overlying the substrate, the first vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the first transistor being coupled to a ground potential; a second vertical transistor formed overlying the first vertical transistor, the first vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the second transistor being connected with the second current electrode of the first transistor to form a first storage node, the gate electrode of the second vertical transistor being a word line, the second current electrode-of the second transistor being coupled to a bit line; and a first resistive device coupled between the first storage node and a power supply conductor.

Claim 28

A semiconductor random access memory device comprising: a substrate; a first vertical transistor formed overlying the substrate, the first vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the first transistor being coupled to a ground potential; a second vertical transistor formed overlying the first vertical transistor, the first vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the second transistor being connected with the second current electrode of the first transistor to form a first storage node, the gate electrode of the second vertical transistor being a word line, the second current electrode-of the second transistor being coupled to a bit line; and a first resistive device coupled between the first storage node and a power supply conductor.

Claim 29

The semiconductor random access memory device of claim 25 further comprising: a third vertical transistor formed overlying the substrate and laterally separated from the first transistor, the third vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the third transistor being coupled to a ground potential; a fourth vertical transistor formed overlying the third vertical transistor, the fourth vertical transistor having a first current electrode underlying a second current electrode wherein a channel region separates the first and second current electrodes, a gate dielectric region is positioned laterally adjacent the channel region and a gate electrode is positioned laterally adjacent the gate dielectric region opposite the channel region, the first current electrode of the fourth transistor being connected with the second current electrode of the third transistor to form a second storage node, the gate electrode of the fourth vertical transistor being another word line, the second current electrode of the fourth transistor being coupled to a complement bit line; a second resistive device being between the second storage node and a power supply conductor; a first conductive interconnect coupling the gate electrode of the first transistor to the second storage node; and a second conductive interconnect coupling the gate electrode of the third transistor to the second storage node.

Claim 30

The semiconductor random access memory device of claim 25 wherein the first resistive device is a device selected from a group consisting of: a resistor, a polysilicon resistor, an amorphous silicon resistor, a P-channel transistor, a P-channel thin film transistor, a P-channel vertical transistor.

Claim 31

A memory device comprising: a substrate; a first vertical device having a first current electrode coupled to a first voltage potential and a second current electrode overlying the first current electrode; a second vertical device overlying the first vertical device and having a first current electrode coupled to the second current electrode of the first vertical device and a second current electrode overlying the first current electrode, the second current electrode of the second vertical device being coupled to a first conductive interconnect layer; a third vertical device coupled between the second current electrode of the first vertical device and a second conductive interconnect layer; a fourth vertical device laterally separated from the first vertical device having a first current electrode coupled to the first voltage potential and a second current electrode overlying the first current electrode; a fifth vertical device overlying the fourth vertical device and having a first current electrode coupled to the second current electrode of the fourth vertical device and a second current electrode overlying the first current electrode, the second current electrode being coupled to a third conductive interconnect layer; and a sixth vertical device coupled between the second current electrode of the fourth vertical device and a fourth conductive interconnect layer.

Claim 32

A memory device comprising: a substrate; a first vertical device having a first current electrode coupled to a first voltage potential and a second current electrode overlying the first current electrode; a second vertical device overlying the first vertical device and having a first current electrode coupled to the second current electrode of the first vertical device and a second current electrode overlying the first current electrode, the second current electrode of the second vertical device being coupled to a first conductive interconnect layer; a third vertical device coupled between the second current electrode of the first vertical device and a second conductive interconnect layer; a fourth vertical device laterally separated from the first vertical device having a first current electrode coupled to the first voltage potential and a second current electrode overlying the first current electrode; a fifth vertical device overlying the fourth vertical device and having a first current electrode coupled to the second current electrode of the fourth vertical device and a second current electrode overlying the first current electrode, the second current electrode being coupled to a third conductive interconnect layer; and a sixth vertical device coupled between the second current electrode of the fourth vertical device and a fourth conductive interconnect layer.

Claim 33

A semiconductor memory device comprising: a substrate having a surface; a first vertical structure at least partially overlying the surface of the substrate, the first vertical structure having a first vertical transistor overlying a first semiconductor device; a second vertical structure at least partially overlying the surface of the substrate and laterally adjacent the first vertical structure, the second vertical structure having a second vertical transistor overlying a second semiconductor device; and electrical interconnects used to: (1) couple the first vertical transistor in series with the first semiconductor device; (2) couple the second vertical transistor in series with the second semiconductor device; and (3) couple the first semiconductor device to the second semiconductor device.

Claim 34

A semiconductor memory device comprising: a substrate having a surface; a first vertical structure at least partially overlying the surface of the substrate, the first vertical structure having a first vertical transistor overlying a first semiconductor device; a second vertical structure at least partially overlying the surface of the substrate and laterally adjacent the first vertical structure, the second vertical structure having a second vertical transistor overlying a second semiconductor device; and electrical interconnects used to: (1) couple the first vertical transistor in series with the first semiconductor device; (2) couple the second vertical transistor in series with the second semiconductor device; and (3) couple the first semiconductor device to the second semiconductor device.

Claim 35

A static random access memory cell comprising: a vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region seperating the first current electrode from the second current electrode, and a gate electrode for selectively changing a conducitivty in the channel region, the gate electode being coupled to a current electrode of another device within the static random access memory cell; a vertical resistive device formed overlying the first vertical transistor, the vertical resistive device having a first end coupled to a power supply conductor and a second end coupled to the second current electrode of the vertical transistor; and an output conductor coupled to the second current electrode of the vertical transistor wherein the output conductor couples the second current electrode of the vertical transistor to a gate electrode of said another device within the static random access memory cell.

Claim 36

A static random access memory cell comprising: a vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region seperating the first current electrode from the second current electrode, and a gate electrode for selectively changing a conducitivty in the channel region, the gate electode being coupled to a current electrode of another device within the static random access memory cell; a vertical resistive device formed overlying the first vertical transistor, the vertical resistive device having a first end coupled to a power supply conductor and a second end coupled to the second current electrode of the vertical transistor; and an output conductor coupled to the second current electrode of the vertical transistor wherein the output conductor couples the second current electrode of the vertical transistor to a gate electrode of said another device within the static random access memory cell.

Claim 37

A static random access memory cell comprising: a vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region seperating the first current electrode from the second current electrode, and a gate electrode for selectively changing a conducitivty in the channel region, the gate electode being coupled to a current electrode of another device within the static random access memory cell; a vertical resistive device formed underlying the first vertical transistor, the vertical resistive device having a first end coupled to a power supply conductor and a second end coupled to the first current electrode of the vertical transistor; and an output conductor coupled to the first current electrode of the vertical transistor wherein the output conductor couples the first current electrode of the vertical transistor to a gate electrode of said another device within the static random access memory cell.

Claim 38

A static random access memory cell comprising: a vertical transistor having a first current electrode, a second current electrode overlying the first current electrode, a channel region seperating the first current electrode from the second current electrode, and a gate electrode for selectively changing a conducitivty in the channel region, the gate electode being coupled to a current electrode of another device within the static random access memory cell; a vertical resistive device formed underlying the first vertical transistor, the vertical resistive device having a first end coupled to a power supply conductor and a second end coupled to the first current electrode of the vertical transistor; and an output conductor coupled to the first current electrode of the vertical transistor wherein the output conductor couples the first current electrode of the vertical transistor to a gate electrode of said another device within the static random access memory cell.