US5218218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and manufacturing method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1992-06-05
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Granted: 1993-06-08
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Expires: 2012-06-05
Abstract
Abstract A semiconductor device includes a second insulator layer (12), a first conductor layer (13) and a second insulator layer (14) stacked in this order on a semiconductor substrate (11), and a trench (15) formed to penetrate the stacked triple layer and extend into the semiconductor substrate. A capacitor is formed at a portion of the trench located in the semiconductor substrate. A transistor is formed directly on this capacitor. The capacitor has one electrode formed of the semiconductor substrate and the other electrode formed of a second conductor layer (18) formed in the trench to open a dielectric film (17). The transistor includes a gate electrode formed of the first conductor layer and source/drain regions (20, 21) of a second conductivity type distributed in the vicinity of the first and second insulator layers in an active layer (19) filling the trench. The drain and source regions of the transistor are formed by thermally diffusing impurities included in the first and second insulator layers into the active layer. Since a region to be added only for isolation is unnecessary in this semiconductor device and a manufacture method thereof, a memory cell area can be reduced, resulting in higher integration of the device.
Inventors
- 👤 Moriaki Akazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:06
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/0383; H10B12/30; H10B12/39; H10B12/395
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
209 words
A semiconductor memory device comprising: a stacked layer including, stacked in the following order on a semiconductor substrate, a first insulator layer, a first conductor layer and a second insulator layer; and a trench formed to penetrate said first insulator layer, said first conductor layer and said second insulator layer and extend into said semiconductor substrate, said trench including a capacitor formed at a portion of said trench located in said semiconductor substrate, and a transistor formed directly on the capacitor, wherein said capacitor includes one electrode formed of said semiconductor substrate and the other electrode formed of a second conductor layer formed on a side surface and a bottom surface of said trench located in said semiconductor substrate, with a dielectric film interposed between the side and bottom surfaces of said second conductor layer and said semiconductor substrate; and said transistor includes a gate electrode formed of said first conductor layer, a gate insulation film formed of an insulator film formed on an inner circumferential surface of said trench located at the position of said first conductor layer, and a source region and a drain region formed in an active layer filling in said trench in the vicinity of said first insulator layer and said second insulator layer.
Claim 2
Dependent Claim
209 words
A semiconductor memory device comprising: a stacked layer including, stacked in the following order on a semiconductor substrate, a first insulator layer, a first conductor layer and a second insulator layer; and a trench formed to penetrate said first insulator layer, said first conductor layer and said second insulator layer and extend into said semiconductor substrate, said trench including a capacitor formed at a portion of said trench located in said semiconductor substrate, and a transistor formed directly on the capacitor, wherein said capacitor includes one electrode formed of said semiconductor substrate and the other electrode formed of a second conductor layer formed on a side surface and a bottom surface of said trench located in said semiconductor substrate, with a dielectric film interposed between the side and bottom surfaces of said second conductor layer and said semiconductor substrate; and said transistor includes a gate electrode formed of said first conductor layer, a gate insulation film formed of an insulator film formed on an inner circumferential surface of said trench located at the position of said first conductor layer, and a source region and a drain region formed in an active layer filling in said trench in the vicinity of said first insulator layer and said second insulator layer.
Claim 3
Dependent Claim
46 words
The semiconductor memory device according to claim 1, wherein said first conductor layer (13) comprises a polysilicon layer including n type impurities; said active layer (19) comprises polysilicon including p type impurities; and said drain and source regions (20 and 21) comprise diffused n type impurities.
Claim 4
Dependent Claim
43 words
The semiconductor memory device according to claim 1, wherein an upper portion of said active layer is deposited over an opening of said trench, and further comprising a third conductor layer formed to make contact with said upper portion of said active layer.
Claim 5
Dependent Claim
38 words
The semiconductor memory device according to claim 3, wherein said third conductor layer (19a) is formed by patterning a doped polysilicon layer piled on said active layer (19) and said second insulator layer (14) in a predetermined pattern.
Claim 6
Dependent Claim
39 words
The semiconductor memory device according to claim 3, wherein said third conductor layer (24) comprises a conductive metal layer patterned to cover the upper portion of said active layer (19) projecting upward above the opening of said trench (15).
Claim 7
Dependent Claim
22 words
The semiconductor memory device according to claim 1, wherein said second conductor layer (18) comprises polysilicon including a predetermined amount of impurities.
Claim 8
Dependent Claim
23 words
The semiconductor memory device according to claim 1, wherein said dielectric film (17) comprises a silicon nitride film and/or a silicon oxide film.
Claim 9
Dependent Claim
74 words
The semiconductor memory device according to claim 1, wherein said first insulator layer and said second insulator layer both include a predetermined amount of impurities having a conductivity type identical to a conductivity type of said drain region and said source region, and said source region is formed by diffusion of the impurities from said first insulator layer, and said drain region is formed by diffusion of the impurities from said second insulator layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |