US4810906A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical inverter circuit
Assignee: Texas Instruments Inc
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Filing: 1988-04-22
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Granted: 1989-03-07
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Expires: 2008-04-22
Abstract
Abstract One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer, and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N- layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.
Inventors
- 👤 Ashwin H. Shah
- 👤 Pallab K. Chatterjee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D64/00; H10D64/60; H10D64/66; H10D64/665; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/837; H10D84/85
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
122 words
A logic gate comprising: a first inverter having an input lead connected to a first input node, a first power lead, a second power lead connected to a first potential and an output lead connected to an output node; a second inverter having an input lead connected to a second input node, a first power lead which is unconnected, a second power lead connected to said first potential and an output lead connected to said output node; and a third inverter having an input lead connected to said second input node, a first power lead connected a second potential, a second power lead connected to said first potential and an output lead connected to said first power lead of said first inverter.
Claim 2
Dependent Claim
122 words
A logic gate comprising: a first inverter having an input lead connected to a first input node, a first power lead, a second power lead connected to a first potential and an output lead connected to an output node; a second inverter having an input lead connected to a second input node, a first power lead which is unconnected, a second power lead connected to said first potential and an output lead connected to said output node; and a third inverter having an input lead connected to said second input node, a first power lead connected a second potential, a second power lead connected to said first potential and an output lead connected to said first power lead of said first inverter.
Claim 3
Dependent Claim
161 words
A logic gate as in claim 1 having said inverters formed on a substrate of a first conductivity type, said inverters comprising: a first channel layer of a second conductivity type formed on the surface of said substrate; a first drain layer of said first conductivity type formed on the surface of said first channel layer; a second drain layer of said second conductivity type formed on the surface of said first drain layer; a second channel layer of said first conductivity type formed on the surface of said second drain layer; a source layer of said second conductivity type formed on the surface of said second channel layer; a conductive gate vertically disposed on an edge perpendicular to the plane of and adjacent to said first and second channel layers, said first and second drain layers and said source layer wherein said gate is insulated from said layers; and a conductive region connected to said first and second drain layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |