Vertical MOS transistor with threshold voltage adjustment

Claim 2

A metal-oxide-semiconductor transistor comprising: A. a substrate, said substrate presenting at least a base region; B. a doped lower source-drain layer of a first conductivity type formed on said base region, and presenting at least a first substantially vertical sidewall extending upwardly from said base region; C. a channel layer, more heavily doped than said lower source-drain layer, of a second conductivity type formed on said lower source-drain layer and presenting at least a second substantially vertical sidewall, said second sidewall extending upwardly from said first sidewall and at least said channel layer including a counterdoped threshold-voltage-adjustment region in at least a margin of said second sidewall; D. an upper source-drain layer of said first conductivity type, less heavily doped than said channel layer, formed on said channel layer and presenting at least a third substantially vertical sidewall, said third sidewall extending upwardly from said second sidewall; E. an insulating oxide layer on at least said base region, first, second and third sidewalls; and F. a gate electrode on said insulating oxide layer opposite at least said channel layer.

Claim 3

The vertical transistor of claim 1 in which said first conductivity type is P-type and said second conductivity type in N-type.

Claim 4

The vertical transistor of claim 1 in which said first conductivity type is N-type and said second conductivity type is P-type.

Claim 5

The vertical transistor of claim 1 in which said threshold-voltage-adjustment region is comprised of P-type material with effective doping level altered by N-type impurity diffusion.

Claim 6

The vertical transistor of claim 1 in which said threshold-voltage-adjustment region is comprised of N-type material with effective doping level altered by P-type impurity diffusion.

Claim 7

The transistor of claim 1 in which said gate electrode is on said insulating oxide layer opposite at least said first, second and third sidewalls.

Claim 8

The transistor of claim 1 in which said gate electrode is on said insulating oxide layer opposite at least said base region, first, second and third sidewalls.

Claim 9

A metal-oxide-semiconductor transistor comprising: A. a semiconductor substrate, said substrate presenting at least a base region; B. a lower source-drain layer of doped semiconductor material of a first conductivity type formed on said base region, and presenting a continuous first substantially vertical sidewall extending upwardly from said base region, said continuous first sidewall having portions defining a trench, and said first sidewall further having a margin; C. a channel layer of semiconductor material, more heavily doped than said lower source-drain layer, of a second conductivity type formed on said lower source-drain layer and presenting a continuous second substantially vertical sidewall in alignment with said first sidewall, said continuous second sidewall having portions defining a trench, and said second sidewall further having a margin; D. an upper source-drain layer of semiconductor material, less heavily doped than said channel layer, of said first conductivity type formed on said channel layer and presenting at least a third substantially vertical sidewall in alignment with said second and first sidewalls, said continuous third sidewall having portions defining a trench, and said third sidewall further having a margin; E. an insulating oxide layer of semiconductor material on at least said base region, first, second and third sidewalls; F. a counterdoped threshold-voltage-adjustment region in all margins; G. a conductive gate electrode formed on said insulating oxide layer opposite at least said base region, first, second and third sidewalls.

Claim 10

A metal-oxide-semiconductor transistor comprising: A. a semiconductor substrate, said substrate presenting at least a base region; B. a lower source-drain layer of doped semiconductor material of a first conductivity type formed on said base region, and presenting a continuous first substantially vertical sidewall extending upwardly from said base region, said continuous first sidewall having portions defining a trench, and said first sidewall further having a margin; C. a channel layer of semiconductor material, more heavily doped than said lower source-drain layer, of a second conductivity type formed on said lower source-drain layer and presenting a continuous second substantially vertical sidewall in alignment with said first sidewall, said continuous second sidewall having portions defining a trench, and said second sidewall further having a margin; D. an upper source-drain layer of semiconductor material, less heavily doped than said channel layer, of said first conductivity type formed on said channel layer and presenting at least a third substantially vertical sidewall in alignment with said second and first sidewalls, said continuous third sidewall having portions defining a trench, and said third sidewall further having a margin; E. an insulating oxide layer of semiconductor material on at least said base region, first, second and third sidewalls; F. a counterdoped threshold-voltage-adjustment region in all margins; G. a conductive gate electrode formed on said insulating oxide layer opposite at least said base region, first, second and third sidewalls.