Insulated gate field effect semiconductor device

Abstract

Abstract PURPOSE:To facilitate control of a threshold voltage and so forth and realize reduction of a leakage current and improvement of dielectric strength by a method wherein a high concentration region and low concentration regions on both sides of the high concentration region are provided in a channel region and those two types of regions have identical conductive type. CONSTITUTION:P<->type regions 23 and 24 have impurity (boron) concentration of, for instance, 1X10<16>cm<-3> and a P<+>type region 20 has impurity concentration of, for instance, 5X10<16>cm<-3>. By forming a high impurity concentration region 20 between low impurity concentration regions 23 and 24 like this, although both regions are composed of P-type semiconductors, the surface potential as an MOS transistor is partially elevated and this elevated surface potential can be made to function as a energy barrier against monority carries. With this constitution, the threshold voltage of the MOS transistor can be controlled. moreover, as this controllability is realized not by increasing the impurity concentration of the substrate but by setting the concentration rather lower, a P-N junction capacitance can be reduced and reduction of a leakage current and improvement of dielectric strength can be also realized.

Inventors

• 👤 Seiji Hashimoto
• 👤 征史 橋本

Bibliographic Details