US4052229A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for preparing a substrate for mos devices of different thresholds
Assignee: Intel Corp
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Filing: 1976-06-25
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Granted: 1977-10-04
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Expires: 1996-06-25
Abstract
Abstract In a substrate, a process for forming a plurality of host regions of different conductivity types and dopant concentration levels. These various host regions include the channels of MOS field-effect devices, thereby providing devices of different voltage thresholds. Overlapping masking and doping provides numerous host regions with a minimum of masking.
Inventors
- 👤 Richard D. Pashley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0128; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
162 words
In the fabrication of MOS devices, a process for preparing a silicon substrate comprising the steps of: a. forming a first masking means over a first area of said substrate; b. subjecting said substrate to a first dopant such that portions thereof other than said first area of said substrate are doped with said first dopant; c. forming a second masking means over a second area of said substrate, said second area being coextensive with a portion of said first area; d. subjecting said substrate to a second dopant such that portions thereof other than said second area of said substrate are doped with said second dopant; said steps (a) through (d) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage; fabricating MOS devices in said host regions, each having a different threshold voltage.
Claim 2
Dependent Claim
162 words
In the fabrication of MOS devices, a process for preparing a silicon substrate comprising the steps of: a. forming a first masking means over a first area of said substrate; b. subjecting said substrate to a first dopant such that portions thereof other than said first area of said substrate are doped with said first dopant; c. forming a second masking means over a second area of said substrate, said second area being coextensive with a portion of said first area; d. subjecting said substrate to a second dopant such that portions thereof other than said second area of said substrate are doped with said second dopant; said steps (a) through (d) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage; fabricating MOS devices in said host regions, each having a different threshold voltage.
Claim 3
Dependent Claim
11 words
The process defined by claim 1 wherein said substrate is p-type.
Claim 4
Dependent Claim
12 words
The process defined by claim 2 wherein said first dopant comprises arsenic.
Claim 5
Dependent Claim
15 words
The process defined by claim 3 wherein said first masking means comprises an oxide layer.
Claim 6
Dependent Claim
12 words
The process defined by claim 4 wherein said second dopant comprises boron.
Claim 7
Dependent Claim
15 words
The process defined by claim 5 wherein said second masking means comprises a photoresist layer.
Claim 8
Dependent Claim
13 words
The process defined by claim 6 wherein said boron dopant is ion implanted.
Claim 9
Dependent Claim
182 words
A process for preparing a p-type silicon substrate such that a plurality of devices of different threshold voltages may be fabricated on said substrate comprising the steps of: a. forming an oxide on said substrate; b. removing a portion of said oxide from said substrate so as to expose a first and second area on said substrate; c. subjecting said substrate to an n-type dopant such that said first and second areas of said substrate are doped; d. forming a masking layer on said substrate, said masking layer covering said second area and a fourth area and said masking layer leaving exposed said first area and a third area; e. subjecting said substrate to a p-type dopant so as to simultaneously dope said first and third areas; said steps (a) through (e) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage; fabricating MOS devices in said host regions, each having a different threshold voltage.
Claim 10
Dependent Claim
182 words
A process for preparing a p-type silicon substrate such that a plurality of devices of different threshold voltages may be fabricated on said substrate comprising the steps of: a. forming an oxide on said substrate; b. removing a portion of said oxide from said substrate so as to expose a first and second area on said substrate; c. subjecting said substrate to an n-type dopant such that said first and second areas of said substrate are doped; d. forming a masking layer on said substrate, said masking layer covering said second area and a fourth area and said masking layer leaving exposed said first area and a third area; e. subjecting said substrate to a p-type dopant so as to simultaneously dope said first and third areas; said steps (a) through (e) resulting in four host regions in said substrate each having a different doping level such that when a field-effect transistor is formed in each of said host regions each such transistor may have a different threshold voltage; fabricating MOS devices in said host regions, each having a different threshold voltage.
Claim 11
Dependent Claim
14 words
The process defined by claim 8 wherein said masking layer comprises a photoresist layer.
Claim 12
Dependent Claim
12 words
The process defined by claim 8 wherein said n-type dopant comprises arsenic.
Claim 13
Dependent Claim
13 words
The process defined by claim 9 wherein said arsenic dopant is ion implanted.
Claim 14
Dependent Claim
12 words
The process defined by claim 8 wherein said p-type dopant comprises boron.
Claim 15
Dependent Claim
12 words
The process defined by claim 11 wherein said dopant ion is implanted.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-03 | 1981-04-04 | 1981-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-03 | 1985-04-04 | 1985-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-03 | 1989-04-04 | 1989-10-04 | $7700.00 | Window Closed / Lapsed |