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US6133077A Expired / Lapsed US ⏱️ 0.0 years remaining

Formation of high-voltage and low-voltage devices on a semiconductor substrate

Assignee: Bell Semiconductor LLC
•
Filing: 1998-01-13
•
Granted: 2000-10-17
•
Expires: 2018-01-13
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Abstract

Abstract A high voltage transistor, formed in a bulk semiconductor material, has a gate region defined by a relatively thick field oxide and a source and drain on opposite sides of the field oxide.

Inventors

  • 👤 Todd A. Randazzo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 09:17
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/025; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/0156; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8314

Claims Analysis

Total Claims: 26
Claim 1
Independent Claim 128 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type; forming gate regions over selected field oxide regions; providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over a field region separating the first and second well regions.
Claim 2
Dependent Claim 128 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type; forming gate regions over selected field oxide regions; providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over a field region separating the first and second well regions.
Claim 3
Dependent Claim 33 words
The process of claim 1 wherein the source and drain regions of the first conductivity type are formed in well regions of both the first and second conductivity type at the same time.
Claim 4
Dependent Claim 20 words
The process of claim 2 wherein gate regions for the high-voltage and low-voltage devices are formed at the same time.
Claim 5
Dependent Claim 23 words
The process of claim 1 wherein wells of the first conductivity type serve, respectively, as drain and source extensions for the high-voltage device.
Claim 6
Dependent Claim 12 words
The process of claim 1 wherein the first conductivity type is n-type.
Claim 7
Dependent Claim 21 words
The process of claim 5 wherein the source and drain regions formed in the wells having n-type conductivity have n+ conductivity.
Claim 8
Dependent Claim 16 words
The process of claim 1 wherein the high-voltage device and the low-voltage device are NMOS devices.
Claim 9
Dependent Claim 17 words
The process of claim 1 wherein low-voltage devices are formed in wells of the second conductivity type.
Claim 10
Dependent Claim 17 words
The process of claim 8 further including forming low-voltage devices in wells of the first conductivity type.
Claim 11
Dependent Claim 15 words
The process of claim 1 wherein the well regions are formed by high-energy ion implantation.
Claim 12
Dependent Claim 22 words
The process of claim 10 wherein the high-energy ion implantation comprises a plurality of implant operations, each implant at a different energy.
Claim 13
Dependent Claim 24 words
The process of claim 1 wherein the field regions are defined by an oxide layer between approximately 1000 angstroms and approximately 6000 angstroms thick.
Claim 14
Dependent Claim 16 words
The process of claim 11 further comprising a step of annealing to activate the implantation regions.
Claim 15
Dependent Claim 173 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type, wherein the source and drain regions formed in the well regions of the first conductivity type are shallower than the well regions in which they are formed; partially etching a field oxide region formed over al field region separating first and second well regions of the first conductivity type; forming gate regions over selected field oxide regions; and providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over the partially-etched field oxide region.
Claim 16
Dependent Claim 173 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type, wherein the source and drain regions formed in the well regions of the first conductivity type are shallower than the well regions in which they are formed; partially etching a field oxide region formed over al field region separating first and second well regions of the first conductivity type; forming gate regions over selected field oxide regions; and providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over the partially-etched field oxide region.
Claim 17
Dependent Claim 33 words
The process of claim 14 wherein the source and drain regions of the first conductivity type are formed in well regions of both the first and second conductivity type at the same time.
Claim 18
Dependent Claim 20 words
The process of claim 15 wherein gate regions for the high-voltage and low-voltage devices are formed at the same time.
Claim 19
Dependent Claim 23 words
The process of claim 14 wherein wells of the first conductivity type serve, respectively, as drain and source extensions for the high-voltage device.
Claim 20
Dependent Claim 178 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type; etching the field oxide region over a selected field region separating first and second well regions of the first conductivity type to substantially eliminate the field oxide on the selected field region; growing an oxide layer of a specified thickness over the selected field region; and forming gate regions over field oxide regions and over the oxide layer grown over the selected field region; and providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over the oxide layer.
Claim 21
Dependent Claim 178 words
A semiconductor device fabrication process comprising: defining field regions and active regions on a surface of a substrate, wherein field oxide regions are provided over the field regions; forming well regions of a first conductivity type and well regions of a second conductivity type in active regions of the substrate, wherein the well regions are separated by field regions; forming source and drain regions of the first conductivity type in well regions of both the first and second conductivity type; etching the field oxide region over a selected field region separating first and second well regions of the first conductivity type to substantially eliminate the field oxide on the selected field region; growing an oxide layer of a specified thickness over the selected field region; and forming gate regions over field oxide regions and over the oxide layer grown over the selected field region; and providing conductive paths to form high-voltage and low-voltage devices, wherein the high-voltage device includes first and second well regions of the first conductivity type and a gate region formed over the oxide layer.
Claim 22
Dependent Claim 33 words
The process of claim 18 wherein the source and drain regions of the first conductivity type are formed in well regions of both the first and second conductivity type at the same time.
Claim 23
Dependent Claim 20 words
The process of claim 19 wherein gate regions for the high-voltage and low-voltage devices are formed at the same time.
Claim 24
Dependent Claim 19 words
The process of claim 14 further including implanting ions below the field region which is to be selectively etched.
Claim 25
Dependent Claim 16 words
The process of claim 14 wherein the step of implanting includes a high-energy ion implantation operation.
Claim 26
Dependent Claim 20 words
The process of claim 21 wherein the high-energy ion implantation and the selective etch are performed using a single mask.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-10-17 2004-04-17 2004-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-10-17 2008-04-17 2008-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-10-17 2012-04-17 2012-10-17 $7700.00 Window Closed / Lapsed

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