US5382820A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage CMOS device to integrate low voltage controlling device
Assignee: United Microelectronics Corp
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Filing: 1993-12-08
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Granted: 1995-01-17
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Expires: 2013-12-08
Abstract
Abstract A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first masking layer on the surface of the substrate; providing openings in the masking layer and implanting dopant ions of a first polarity into the surface of the substrate in a set of first regions selected in the substrate and the well forming a second masking layer on the surface of the substrate; implanting dopant ions of a second polarity through a second mask in other regions selected in the well and the substrate; removal of the second masking layer; formation of field oxide structures over the first and second regions; forming gate oxide layers above the exposed portions of the first and second central regions; and formation of conductive gate structures over the gate oxide layers.
Inventors
- 👤 Sheng-Hsing Yang
- 👤 Nai-Jen Yeh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
145 words
A semiconductor device comprising a) a N-silicon substrate with an N- impurity, b) a P-well with a P- impurity, c) dopant ions of P- polarity in the surface of said substrate in a set of P- regions selected in said substrate and said well, d) dopant ions of an N- polarity implanted in N- regions between said P- regions in said well and on either side of said P- regions in said N-silicon substrate, e) field oxide structures over said P- and N- regions, f) gate oxide layers above the exposed portions of said N- silicon substrate and said P-well, g) conductive gate structures over said gate oxide layers between said N- regions in said well and between said P-regions in said N- substrate, and h) an implanted P- isolation region in said P-well and an implant of an N- isolation region in said N-substrate.
Claim 2
Dependent Claim
145 words
A semiconductor device comprising a) a N-silicon substrate with an N- impurity, b) a P-well with a P- impurity, c) dopant ions of P- polarity in the surface of said substrate in a set of P- regions selected in said substrate and said well, d) dopant ions of an N- polarity implanted in N- regions between said P- regions in said well and on either side of said P- regions in said N-silicon substrate, e) field oxide structures over said P- and N- regions, f) gate oxide layers above the exposed portions of said N- silicon substrate and said P-well, g) conductive gate structures over said gate oxide layers between said N- regions in said well and between said P-regions in said N- substrate, and h) an implanted P- isolation region in said P-well and an implant of an N- isolation region in said N-substrate.
Claim 3
Dependent Claim
23 words
A device in accordance with claim 1 with said conductive gate structures extending over the top of said field oxide layers juxtaposed therewith.
Claim 4
Dependent Claim
14 words
A device in accordance with claim 2 with said conductive gate structures comprising polysilicon.
Claim 5
Dependent Claim
20 words
A device in accordance with claim 1 with an N- grade region formed after formation of said conductive gate structures.
Claim 6
Dependent Claim
18 words
A device in accordance with claim 4 with an N+ diffusion region formed after said N- grade region.
Claim 7
Dependent Claim
16 words
A device in accordance with claim 5 with a P+ diffusion formed after said N+ diffusion.
Claim 8
Dependent Claim
17 words
A device in accordance with claim 6 with a contact area formed down to said P+ diffusion.
Claim 9
Dependent Claim
21 words
A device in accordance with claim 7 with metal deposited into said contact area for electrical connection to said P+ diffusion.
Claim 10
Dependent Claim
20 words
A device in accordance with claim 7 with oxide deposited, with reflow and with densification performed after said P+ diffusion.
Claim 11
Dependent Claim
31 words
A device in accordance with claim 9 with a contact area formed down to said P+ diffusion, and metal deposited into said contact area for electrical connection to said P+ diffusion.
Claim 12
Dependent Claim
227 words
A semiconductor device fabricated by the method comprising a) applying an impurity of a N- polarity to a silicon substrate, b) forming a P-well by applying an impurity of P- polarity to a region in said silicon substrate, c) forming a first masking layer on the surface of said substrate, d) providing openings in said masking layer and implanting P- dopant ions into the surface of said substrate in a set of P- regions selected in said substrate and said well, e) forming a second masking layer on the surface of said substrate, f) implanting dopant ions of an N- polarity through a second mask in N- regions selected in said P- well and said substrate, g) removal of said second masking layer, h) formation of field oxide structures over said P- and N- regions, i) forming gate oxide layers above the exposed portions of said N-substrate and said P-well regions, j) formation of conductive gate structures over said gate oxide layers, and k) implanting a P- isolation region from about 3×10 13 /cm 2 to about 9×10 13 /cm 2 at an energy from about 20 keV to about 50 keV in said P-well and implanting an N- isolation region from about 1.5×10 12 /cm 2 to about 5.5×10 12 /cm 2 at an energy from about 120 keV to about 180 keV in said N-substrate.
Claim 13
Dependent Claim
227 words
A semiconductor device fabricated by the method comprising a) applying an impurity of a N- polarity to a silicon substrate, b) forming a P-well by applying an impurity of P- polarity to a region in said silicon substrate, c) forming a first masking layer on the surface of said substrate, d) providing openings in said masking layer and implanting P- dopant ions into the surface of said substrate in a set of P- regions selected in said substrate and said well, e) forming a second masking layer on the surface of said substrate, f) implanting dopant ions of an N- polarity through a second mask in N- regions selected in said P- well and said substrate, g) removal of said second masking layer, h) formation of field oxide structures over said P- and N- regions, i) forming gate oxide layers above the exposed portions of said N-substrate and said P-well regions, j) formation of conductive gate structures over said gate oxide layers, and k) implanting a P- isolation region from about 3×10 13 /cm 2 to about 9×10 13 /cm 2 at an energy from about 20 keV to about 50 keV in said P-well and implanting an N- isolation region from about 1.5×10 12 /cm 2 to about 5.5×10 12 /cm 2 at an energy from about 120 keV to about 180 keV in said N-substrate.
Claim 14
Dependent Claim
23 words
A device in accordance with claim 11 wherein said conductive gate structures extend over the top of said field oxide layers juxtaposed therewith.
Claim 15
Dependent Claim
14 words
A device in accordance with claim 12 wherein said conductive gate structures comprise polysilicon.
Claim 16
Dependent Claim
47 words
A device in accordance with claim 11 wherein an N- grade region is formed after formation of said conductive gate structures from about 2×10 13 /cm 2 to about 8×10 13 /cm 2 at an energy from about 120 keV to about 180 keV in said P-well.
Claim 17
Dependent Claim
34 words
A device in accordance with claim 14 wherein an N+ diffusion region is formed after said N- grade region of arsenic from about 3×10 15 /cm 2 to about 5×10 15 /cm 2 .
Claim 18
Dependent Claim
43 words
A device in accordance with claim 15 wherein a P+ diffusion from about 3×10 15 /cm 2 to about 5×10 15 /cm 2 at an energy from about 60 keV to about 120 keV in said P-well is formed after said N+ diffusion.
Claim 19
Dependent Claim
18 words
A device in accordance with claim 16 wherein a contact area is formed down to said P+ diffusion.
Claim 20
Dependent Claim
22 words
A device in accordance with claim 17 wherein metal is deposited into said contact area for electrical connection to said P+ diffusion.
Claim 21
Dependent Claim
22 words
A device in accordance with claim 17 wherein oxide is deposited, reflow is performed and densification is performed after said P+ diffusion.
Claim 22
Dependent Claim
33 words
A device in accordance with claim 19 wherein a contact area is formed down to said P+ diffusion, and metal is deposited into said contact area for electrical connection to said P+ diffusion.
Claim 23
Independent Claim
226 words
A method of fabrication of an semiconductor device comprising a) applying an impurity of N- polarity to a silicon substrate, b) forming a P- well by applying an impurity of an opposite polarity to a region in said silicon substrate, c) forming a first masking layer on the surface of said substrate, d) providing openings in said masking layer and implanting P- dopant ions into the surface of said substrate in a set of P- regions selected in said substrate and said well e) forming a second masking layer on the surface of said substrate, f) implanting N- dopant ions of an N- polarity through a second mask in second regions selected in said P-well and said substrate, g) removal of said second masking layer, h) formation of field oxide structures over said first and second regions, i) forming gate oxide layers between said N- regions and said P- regions, j) formation of conductive gate structures over said gate oxide layers, and k) implanting a P- isolation region from about 3×10 13 /cm 2 to about 9×10 13 /cm 2 at an energy from about 20 keV to about 50 keV in said P-well and implanting an N- isolation region from about 1.5×10 12 /cm 2 to about 5.5×10 12 /cm 2 at an energy from about 120 keV to about 180 keV in said N-substrate.
Claim 24
Independent Claim
226 words
A method of fabrication of an semiconductor device comprising a) applying an impurity of N- polarity to a silicon substrate, b) forming a P- well by applying an impurity of an opposite polarity to a region in said silicon substrate, c) forming a first masking layer on the surface of said substrate, d) providing openings in said masking layer and implanting P- dopant ions into the surface of said substrate in a set of P- regions selected in said substrate and said well e) forming a second masking layer on the surface of said substrate, f) implanting N- dopant ions of an N- polarity through a second mask in second regions selected in said P-well and said substrate, g) removal of said second masking layer, h) formation of field oxide structures over said first and second regions, i) forming gate oxide layers between said N- regions and said P- regions, j) formation of conductive gate structures over said gate oxide layers, and k) implanting a P- isolation region from about 3×10 13 /cm 2 to about 9×10 13 /cm 2 at an energy from about 20 keV to about 50 keV in said P-well and implanting an N- isolation region from about 1.5×10 12 /cm 2 to about 5.5×10 12 /cm 2 at an energy from about 120 keV to about 180 keV in said N-substrate.
Claim 25
Dependent Claim
23 words
A method in accordance with claim 21 wherein said conductive gate structures extend over the top of said field oxide layers juxtaposed therewith.
Claim 26
Dependent Claim
14 words
A method in accordance with claim 22 wherein said conductive gate structures comprise polysilicon.
Claim 27
Dependent Claim
47 words
A method in accordance with claim 21 wherein an N- grade region is formed after formation of said conductive gate structures from about 2×10 13 /cm 2 to about 8×10 13 /cm 2 at an energy from about 120 keV to about 180 keV in said P-well.
Claim 28
Dependent Claim
34 words
A method in accordance with claim 24 wherein an N+ diffusion region is formed after said N- grade region of arsenic from about 3×10 15 /cm 2 to about 5×10 15 /cm 2 .
Claim 29
Dependent Claim
43 words
A method in accordance with claim 5 wherein a P+ diffusion from about 3×10 15 /cm 2 to about 5×10 15 /cm 2 at an energy from about 60 keV to about 120 keV in said P-well is formed after said N+ diffusion.
Claim 30
Dependent Claim
18 words
A method in accordance with claim 6 wherein a contact area is formed down to said P+ diffusion.
Claim 31
Dependent Claim
22 words
A method in accordance with claim 27 wherein metal is deposited into said contact area for electrical connection to said P+ diffusion.
Claim 32
Dependent Claim
22 words
A method in accordance with claim 27 wherein oxide is deposited, reflow is performed and densification is performed after said P+ diffusion.
Claim 33
Dependent Claim
33 words
A method in accordance with claim 29 wherein a contact area is formed down to said P+ diffusion, and metal is deposited into said contact area for electrical connection to said P+ diffusion.
Claim 34
Dependent Claim
56 words
A device in accordance with claim 1, wherein a low voltage implant of a P-field and an N-field produced a high voltage device region (P-drift, P-isolation, N-drift, N-isolation) for controlling the P- implant and the N- implant to meet high voltage device requirements, while eliminating the requirement for an additional mask to produce the desired results.
References Cited (Backward Citations)
US5128739A
Cited
US5008722A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |