US5128739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS type semiconductor device formed in a semiconductor substrate having a well region
Assignee: Fujitsu Ltd
•
Filing: 1990-11-19
•
Granted: 1992-07-07
•
Expires: 2010-11-19
Abstract
Abstract In order to provide semiconductor devices having a high switching speed and high packing density of the circuit elements, a p-MOSFET of a CMOS IC is formed on an n-type well which has a higher impurity concentration compared with that of the n-type substrate region and which is formed at selected portions under the p-MOSFET. In order to decrease the capacitance of the source and drain of the p-MOSFET, the n-type well regions are selectively formed only at portions under the gate electrode and the field insulating layer, and a junction of the p + -type drain and source region is formed directly on a part of the n - -type substrate region. As a result, the latch-up phenomenon can be suppressed and the junction capacitance of the devices becomes smaller. Therefore, the switching speed and the packing density of the CMOS IC are improved.
Inventors
- 👤 Takehide Shirato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
330 words
A high speed complementary metal oxide semiconductor (C-MOS) field effect transistor (FET) for high speed operation having a short channel length, comprising: a semiconductor substrate having a first conductivity type and a first impurity concentration; a field insulation layer formed over said substrate for separating elements formed in said substrate from each other; a first well region formed in said substrate, said first well region having a second conductivity type which is opposite the first conductivity type; a first field effect transistor formed in said first well region, having a first conductivity type channel and having a channel stopper formed in said first well region beneath said field insulation layer, said channel stopper having an impurity concentration higher than the impurity concentration of said first well region; a second well region formed in portions of said substrate and adjoining said first well region, and having a first conductivity type and a higher impurity concentration than said first impurity concentration; a second field effect transistor formed in said second well region, having a second conductivity type channel, having a source region and having a drain region, said second well region extending under said channel of said second FET and under portions of said source region and said drain region where said source and drain regions are in contact with said field insulation layer, said second well region further extending under said field insulation layer adjacent said portions of said source and drain regions and having a sufficiently high impurity concentration to provide a channel stop function under said field insulation layer, said second well region being eliminated from a bottom portion of at least one of said source and drain regions of said second field effect transistor so as to reduce the associated junction capacitance; and a lateral diffusion region adjacent to said drain region and said source region of said second field effect transistor, said lateral diffusion region having a lower impurity concentration than that of said second well region.
Claim 2
Dependent Claim
330 words
A high speed complementary metal oxide semiconductor (C-MOS) field effect transistor (FET) for high speed operation having a short channel length, comprising: a semiconductor substrate having a first conductivity type and a first impurity concentration; a field insulation layer formed over said substrate for separating elements formed in said substrate from each other; a first well region formed in said substrate, said first well region having a second conductivity type which is opposite the first conductivity type; a first field effect transistor formed in said first well region, having a first conductivity type channel and having a channel stopper formed in said first well region beneath said field insulation layer, said channel stopper having an impurity concentration higher than the impurity concentration of said first well region; a second well region formed in portions of said substrate and adjoining said first well region, and having a first conductivity type and a higher impurity concentration than said first impurity concentration; a second field effect transistor formed in said second well region, having a second conductivity type channel, having a source region and having a drain region, said second well region extending under said channel of said second FET and under portions of said source region and said drain region where said source and drain regions are in contact with said field insulation layer, said second well region further extending under said field insulation layer adjacent said portions of said source and drain regions and having a sufficiently high impurity concentration to provide a channel stop function under said field insulation layer, said second well region being eliminated from a bottom portion of at least one of said source and drain regions of said second field effect transistor so as to reduce the associated junction capacitance; and a lateral diffusion region adjacent to said drain region and said source region of said second field effect transistor, said lateral diffusion region having a lower impurity concentration than that of said second well region.
Claim 3
Dependent Claim
238 words
A high speed complementary metal oxide semiconductor (C-MOS) field effect transistor (FET) for high speed operation having a short channel length, comprising: a semiconductor substrate having a first conductivity type and a first impurity concentration; a field insulation layer formed over said substrate for separating elements formed in said substrate from each other; a first well region formed in said substrate, said first well region having a second conductivity type opposite the first conductivity type; a first field effect transistor formed in said first well region, having a first conductivity type channel and having a channel stopper formed in said first well region beneath said field insulation layer, said channel stopper having an impurity concentration higher than the impurity concentration of said first well region; a second well region formed in portions of said substrate and adjoining said first well region, and having a first conductivity type and a higher impurity concentration than said first impurity concentration; a second field effect transistor formed in said second well region, having a second conductivity type channel, having a source region and having a drain region, said second well region extending under said channel and said source region and under portions of said drain region of said second FET; and a lateral diffusion region adjacent to said drain region of said second field effect transistor, said lateral diffusion region having a lower impurity concentration than that of said second well region.
Claim 4
Dependent Claim
238 words
A high speed complementary metal oxide semiconductor (C-MOS) field effect transistor (FET) for high speed operation having a short channel length, comprising: a semiconductor substrate having a first conductivity type and a first impurity concentration; a field insulation layer formed over said substrate for separating elements formed in said substrate from each other; a first well region formed in said substrate, said first well region having a second conductivity type opposite the first conductivity type; a first field effect transistor formed in said first well region, having a first conductivity type channel and having a channel stopper formed in said first well region beneath said field insulation layer, said channel stopper having an impurity concentration higher than the impurity concentration of said first well region; a second well region formed in portions of said substrate and adjoining said first well region, and having a first conductivity type and a higher impurity concentration than said first impurity concentration; a second field effect transistor formed in said second well region, having a second conductivity type channel, having a source region and having a drain region, said second well region extending under said channel and said source region and under portions of said drain region of said second FET; and a lateral diffusion region adjacent to said drain region of said second field effect transistor, said lateral diffusion region having a lower impurity concentration than that of said second well region.
References Cited (Backward Citations)
GB1153428A
Cited
US3751722A
Cited
US3946419A
Cited
US4104784A
Cited
JPS5380172A
Cited
DE2801085A1
Cited
US4132998A
Cited
JPS54136275A
Cited
JPS55111171A
Cited
US4306916A
Cited
EP0057024A1
Cited
US4435895A
Cited
US4468852A
Cited
US4480375A
Cited
US4633289A
Cited
US4599789A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |