Latch-up immune, multiple retrograde well high density CMOS FET

Claim 2

A CMOS comprising: (a) a substrate; (b) a well region within and adjacent a surface of said substrate, said well region having a multiple retrograde doping density profile comprising two retrograde peaks; and (c) source and drain regions within said well region and adjacent the surface of said substrate, said source and drain regions having associated therewith a greater density of residual defects than average within said well region, said defects being generally associated with the deepest portions of said source and drain regions and the immediately underlying portions of said regions, respectively, the double retrograde doping profile extending for substantially the entire depth of the well below the source and drain region with a doping density sufficient to substantially inhibit latch-up of the FET.

Claim 3

The CMOS FET of claim 1 wherein said residual defects are substantially present only in said well region source and drain regions and the immediately underlying portions of said well region so that the operation of said CMOS FET is substantially unaffected.

Claim 4

The CMOS FET of claim 2 wherein the product of the depth of said well region and the average doping density of said well region is greater than approximately 1.0×10 13 cm -2 and wherein the depth of said well region is less than approximately 3.0 micrometers.

Claim 5

The CMOS FET of claim 3 wherein the total field strength of the electric fields induced in said well region, respectively due to each retrograde peak of the multiple retrograde doping density profile thereof, is greater than approximately 800 V/cm.

Claim 6

A CMOS structure including at least a first and a second active device having operationally associated active channels of a first and a second conductivity type, respectively, formed at a surface of a substrate of said first conductivity type, said first active device being further formed at a surface of a well region of said second conductivity type, said first and second active devices being closely disposed at the surface of said substrate so as to be electrically coupled by a vertical parasitic bipolar transistor associated with said first active device and a lateral parasitic bipolar transistor associated with said second active device in a gain feedback loop, wherein said improvement comprises: (a) said well region having a multiple retrograde dopant profile comprising two retrograde peaks, the double retrograde doping profile extending for substantially the entire depth of the well below the first active device with a doping density sufficient to substantially inhibit latch-up of the structure; and (b) residual defects, acting as charge carrier recombination centers, distributed within said source and drain regions of said first active device and within that portion of said well region immediately underlying said source and drain regions of said first active device such that the gain of said feedback loop is substantially reduced.

Claim 7

A CMOS structure including at least a first and a second active device having operationally associated active channels of a first and a second conductivity type, respectively, formed at a surface of a substrate of said first conductivity type, said first active device being further formed at a surface of a well region of said second conductivity type, said first and second active devices being closely disposed at the surface of said substrate so as to be electrically coupled by a vertical parasitic bipolar transistor associated with said first active device and a lateral parasitic bipolar transistor associated with said second active device in a gain feedback loop, wherein said improvement comprises: (a) said well region having a multiple retrograde dopant profile comprising two retrograde peaks, the double retrograde doping profile extending for substantially the entire depth of the well below the first active device with a doping density sufficient to substantially inhibit latch-up of the structure; and (b) residual defects, acting as charge carrier recombination centers, distributed within said source and drain regions of said first active device and within that portion of said well region immediately underlying said source and drain regions of said first active device such that the gain of said feedback loop is substantially reduced.

Claim 8

The CMOS FET of claim 6 wherein the cumulative intensity of an electric field associated with each retrograde peak of the multiple retrograde doping density profile and the density of said residual defects is sufficient to reduce the gain of said feedback loop to approximately one or less.