US4599789A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making twin well VLSI CMOS
Assignee: Intersil Corp
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Filing: 1984-06-15
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Granted: 1986-07-15
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Expires: 2004-06-15
Abstract
Abstract CMOS devices are formed in self-aligned wells in a substrate produced by a two mask, one photolithographic step process wherein the first mask is used as a template to form the second inverse mask of substantially equal thickness. The gates are used as alignment mask for shallow source and drain regions and subsequently formed lateral gate spacers are used as alignment mask for deep source and drain regions. Exposed source and drain regions and silicon gates have silicide formed thereon by a non-selective process.
Inventors
- 👤 John T. Gasner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 03:42
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
289 words
A method for forming complementary insulated gate field effect transistors comprising: forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface separated laterally by said insert; forming a first mask layer having a first opening on said substrate; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said first opening to form simultaneously a second conductivity type well in said second mesa having a higher impurity concentration at the bottom of said well and guard ring under a portion of said insert; forming a second mask on said surface, the reverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form simultaneously a first conductivity type well in said first mesa having a high impurity concentration at the bottom of said well and a guard ring under a portion of said insert; forming a gate insulative layer on said substrate; forming first and second gates on said gate insulative layer over said first and second wells, respectively; introducing second conductivity type impurities into said first well using said first gate as a mask to form shallow source and drain regions; introducing first conductivity type impurities into said second well using said second gate on a mask to form shallow source and drain regions; forming insulative spacers extending lateral from said first and second gates over said source and drain regions; introducing sell using said second gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions.
Claim 2
Independent Claim
289 words
A method for forming complementary insulated gate field effect transistors comprising: forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface separated laterally by said insert; forming a first mask layer having a first opening on said substrate; introducing second conductivity type impurities opposite said first conductivity type into said substrate through said first opening to form simultaneously a second conductivity type well in said second mesa having a higher impurity concentration at the bottom of said well and guard ring under a portion of said insert; forming a second mask on said surface, the reverse image of said first mask using said first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form simultaneously a first conductivity type well in said first mesa having a high impurity concentration at the bottom of said well and a guard ring under a portion of said insert; forming a gate insulative layer on said substrate; forming first and second gates on said gate insulative layer over said first and second wells, respectively; introducing second conductivity type impurities into said first well using said first gate as a mask to form shallow source and drain regions; introducing first conductivity type impurities into said second well using said second gate on a mask to form shallow source and drain regions; forming insulative spacers extending lateral from said first and second gates over said source and drain regions; introducing sell using said second gate and spacers as a mask to form deep source and drain regions having a greater depth than said shallow source and drain regions.
Claim 3
Dependent Claim
78 words
A method according to claim 1 wherein said first and second gates and said substrate are formed of silicon; and further including forming oxide regions between said wells before forming said source and drain regions, non-selectively forming a silicide forming material over said substrate after forming said deep source and drain regions, heating to form a metal silicide on said gate and source and drain regions, and removing said silicide forming material from said spacers and oxide regions.
Claim 4
Dependent Claim
97 words
A method according to claim 1 wherein: introducing impurities to form said shallow source and drain regions in said first well is performed using said gates only as a mask; introducing impurities to form said shallow source and drain regions in said second well includes forming a mask covering said first well; introducing impurities to form said deep source and drain regions in said second well includes forming a mask covering said first well; and introducing impurities to form said deep source and drain regions in said first well includes forming a mask covering said second well.
Claim 5
Dependent Claim
97 words
A method according to claim 1 wherein: introducing impurities to form said shallow source and drain regions in said first well includes forming a mask covering said second well; introducing impurities to form said shallow source and drain regions in said second well includes forming a mask covering said first well; introducing impurities to form said deep source and drain regions in said first well is performed using said gate only as a mask; and introducing impurities to form said deep source and drain regions in said second well includes forming a mask covering said first well.
Claim 6
Dependent Claim
15 words
A method according to claim 1 wherein all said impurity introduction steps include ion implantation.
Claim 7
Dependent Claim
37 words
A method according to claim 1 including forming oxide inserts in said substrate before forming said first mask; and wherein said impurities are introduced to form said first and second wells which extend below said oxide inserts.
Claim 8
Dependent Claim
53 words
A method according to claim 1 wherein forming said second mask includes: applying a second mask layer to at least fill any opening in said first mask; removing said second mask layer until a portion of said first mask is exposed; and selectively removing said first mask with any superimposed second mask layer.
Claim 9
Dependent Claim
25 words
A method according to claim 6 wherein forming said oxide inserts includes etching said substrate to form insert trenches and depositing oxide filling said trenches.
Claim 10
Dependent Claim
40 words
A method according to claim 8 wherein said oxide is deposited overfilling said trenches and including applying a planarization layer on said oxide and etching said planarization layer and oxide layer to form oxide inserts substantially planar with said substrate.
Claim 11
Independent Claim
233 words
A method for forming complementary insulated gate field effect transistors comprising: a forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface separated laterally by said insert; forming a first mask layer having an opening over said second mesa and a portion of said insulative insert; introducing second conductive type impurities opposite said first conductivity type into said substrate through said opening to form a second conductivity well in said second mesa and under a portion of said insert and having a higher impurity concentration at the bottom of said well; forming a second mask on said surface, the inverse image of said first mask using sid first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form a first conductivity type well in said first mesa and under the remainder of said insert and having a higher impurity concentration at the bottom of said well; removing said second mask; forming a gate insulative layer on said mesas; forming a first and second gate on said insulative layer on said first and second mesas respectively; introducing first conductivity type impurities into said second mesa to form source and drain regions; and introducing second conductivity type impurities into said first mesa to form source and drain regions.
Claim 12
Independent Claim
233 words
A method for forming complementary insulated gate field effect transistors comprising: a forming at least one insulative insert in a substrate of a first conductivity type to form at least a first and second mesas in said surface separated laterally by said insert; forming a first mask layer having an opening over said second mesa and a portion of said insulative insert; introducing second conductive type impurities opposite said first conductivity type into said substrate through said opening to form a second conductivity well in said second mesa and under a portion of said insert and having a higher impurity concentration at the bottom of said well; forming a second mask on said surface, the inverse image of said first mask using sid first mask as a template; introducing first conductivity type impurities into said substrate through an opening in said second mask to form a first conductivity type well in said first mesa and under the remainder of said insert and having a higher impurity concentration at the bottom of said well; removing said second mask; forming a gate insulative layer on said mesas; forming a first and second gate on said insulative layer on said first and second mesas respectively; introducing first conductivity type impurities into said second mesa to form source and drain regions; and introducing second conductivity type impurities into said first mesa to form source and drain regions.
Claim 13
Dependent Claim
14 words
A method according to claim 10, wherein said wells are formed by ion implantation.
Claim 14
Dependent Claim
24 words
A method according to claim 10, wherein forming said inserts include etching said substrate to form insert trenches and depositing oxide filling said trenches.
Claim 15
Dependent Claim
17 words
A method according to claim 11, wherein said source and drain regions are formed by ion implantation.
Claim 16
Dependent Claim
40 words
A method according to claim 12, wherein said oxide is deposited overfilling said trenches and including applying a planarization layer on said oxide and etching said planarization layer and oxide layer to form oxide inserts substantially planar with said substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-07-14 | 1990-01-13 | 1990-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-07-14 | 1994-01-13 | 1994-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-07-14 | 1998-01-13 | 1998-07-15 | $7700.00 | Window Closed / Lapsed |