US5438005A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Deep collection guard ring
Assignee: Winbond Electronics Corp
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Filing: 1994-04-13
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Granted: 1995-08-01
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Expires: 2014-04-13
Abstract
Abstract A CMOS device is provided with a deep collector guard ring. The guard ring is formed by thermally deep diffusing impurities from a poly layer into the surface of a well beneath the poly layer. The guard ring can thus be easily manufactured using CMOS compatible fabrication processes to a depth which is greater than the source and drain regions of the CMOS device.
Inventors
- 👤 Wen-Yueh Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:27
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
131 words
A CMOS manufacturing process comprising the steps of: forming an N-well and a P-well in a substrate, forming a polysilicon layer having at least a portion which is heavily doped with a first conductivity type in a vicinity of at least a portion of a surface of one of said wells, forming a guard ring by deep diffusing impurities from said polysilicon layer portion into said surface of said one well, and after said step of forming a guard ring, forming P + source and drain regions in said N-well and N + source and drain regions in said P-well, said drains in said N-well and said P-well being separated from each other by said guard ring, wherein said guard ring has a depth greater than said source and drain regions.
Claim 2
Dependent Claim
131 words
A CMOS manufacturing process comprising the steps of: forming an N-well and a P-well in a substrate, forming a polysilicon layer having at least a portion which is heavily doped with a first conductivity type in a vicinity of at least a portion of a surface of one of said wells, forming a guard ring by deep diffusing impurities from said polysilicon layer portion into said surface of said one well, and after said step of forming a guard ring, forming P + source and drain regions in said N-well and N + source and drain regions in said P-well, said drains in said N-well and said P-well being separated from each other by said guard ring, wherein said guard ring has a depth greater than said source and drain regions.
Claim 3
Dependent Claim
54 words
The process of claim further comprising the steps of: forming a thin oxide layer on said wells, forming at least one window in said thin layer oxide to expose a portion of said one well, forming said silicon polylayer portion over said thin oxide layer and on said exposed portion of said one well.
Claim 4
Dependent Claim
43 words
The process of claim 2 further comprising the steps of: after forming said guard ring, removing portions of said poly silicon layer except said portion above said window and at least one portion between said drain and said source of said one well.
Claim 5
Dependent Claim
71 words
The process of claim 1 wherein a second portion of said poly layer is formed on at least a portion of a surface of another one of said wells, which second poly layer portion is heavily doped with a second conductivity type, said method further comprising the step of: forming a second guard ring by deep diffusing impurities from said second poly layer portion into said surface of said other well.
Claim 6
Dependent Claim
42 words
The process of claim 1 wherein said step of forming said source and drain regions further comprises the step of simultaneously forming a second guard ring in another one of said wells while forming said source and drain in said one well.
Claim 7
Dependent Claim
20 words
The process of claim 1 wherein said one well is said N-well and wherein said first conductivity type is N.
Claim 8
Dependent Claim
41 words
The process of claim 1 wherein said guard ring collects a base current of a transistor formed in another one of said wells by said source and drain of said other well and a bulk of material of said other well.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-31 | 1999-01-30 | 1999-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-31 | 2003-01-30 | 2003-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-31 | 2007-01-30 | 2007-08-01 | $7700.00 | Window Closed / Lapsed |