Method of producing a semiconductor device having two MIS transistor circuits

Claim 1

A method of producing a semiconductor device including, on a surface side of a semiconductor substrate, a first MIS transistor circuit portion with a first-conducting-type first MIS portion and a second-conducting-type second MIS portion, and a second MIS transistor circuit portion with a first-conducting-type third MIS portion and a second-conducting-type fourth MIS portion, comprising: a first step of, after forming a first insulating film on said surface side of said semiconductor substrate, forming a first polycrystalline silicon layer on a surface side of said first insulating film without being in contact with any resist layer; a second step of leaving portions of said first polycrystalline silicon layer, in which impurities have not been injected, in respective gate electrode formation regions of said first conducting-type third MIS portion and said second-conducting-type fourth MIS portion of said second MIS transistor circuit portion by etching said first polycrystalline silicon layer; a third step of removing portions of said first insulating film in gate insulating film formation regions of said first-conducting-type first MIS portion and said second-conducting-type second MIS portion of said first MIS transistor circuit portion; a fourth step of, after forming a second insulating film on a surface side of said substrate, forming a second polycrystalline silicon layer on a Surface side of said second insulating film; and a fifth step of leaving portions of said second polycrystalline silicon layer in respective gate electrode formation regions of said first-conducting-type first MIS portion and said second-conducting-type second MIS portion of said first MIS transistor circuit portion by etching said second polycrystalline silicon layer, wherein impurities are introduced at the same time and for the first time as a step of introducing impurities for forming a source diffusion region and a drain diffusion region of said third MIS portion, into said first polycrystalline silicon layer left in the second step in said gate electrode formation region of said first-conducting-type third MIS portion of said second MIS transistor circuit portion, and impurities are introduced at the same time and for the first time as a step for introducing impurities for forming a source diffusion legion and a drain diffusion region of said fourth MIS portion, into said polycrystalline silicon layer left in the second step in said gate electrode formation region of said second-conducting-type fourth MIS portion.

Claim 2

A method of producing a semiconductor device including, on a surface side of a semiconductor substrate, a first MIS transistor circuit portion with a first-conducting-type first MIS portion and a second-conducting-type second MIS portion, and a second MIS transistor circuit portion with a first-conducting-type third MIS portion and a second-conducting-type fourth MIS portion, comprising: a first step of, after forming a first insulating film on said surface side of said semiconductor substrate, forming a first polycrystalline silicon layer on a surface side of said first insulating film without being in contact with any resist layer; a second step of leaving portions of said first polycrystalline silicon layer, in which impurities have not been injected, in respective gate electrode formation regions of said first conducting-type third MIS portion and said second-conducting-type fourth MIS portion of said second MIS transistor circuit portion by etching said first polycrystalline silicon layer; a third step of removing portions of said first insulating film in gate insulating film formation regions of said first-conducting-type first MIS portion and said second-conducting-type second MIS portion of said first MIS transistor circuit portion; a fourth step of, after forming a second insulating film on a surface side of said substrate, forming a second polycrystalline silicon layer on a Surface side of said second insulating film; and a fifth step of leaving portions of said second polycrystalline silicon layer in respective gate electrode formation regions of said first-conducting-type first MIS portion and said second-conducting-type second MIS portion of said first MIS transistor circuit portion by etching said second polycrystalline silicon layer, wherein impurities are introduced at the same time and for the first time as a step of introducing impurities for forming a source diffusion region and a drain diffusion region of said third MIS portion, into said first polycrystalline silicon layer left in the second step in said gate electrode formation region of said first-conducting-type third MIS portion of said second MIS transistor circuit portion, and impurities are introduced at the same time and for the first time as a step for introducing impurities for forming a source diffusion legion and a drain diffusion region of said fourth MIS portion, into said polycrystalline silicon layer left in the second step in said gate electrode formation region of said second-conducting-type fourth MIS portion.