Method of making a semiconductor device having DRAM cells and floating gate memory cells

Claim 1

A method of manufacturing a semiconductor device having dynamic type memory elements and non-volatile memory elements on a semiconductor substrate, each of the dynamic type memory elements having a capacitance element which comprises a first electrode, a second electrode, and a dielectric film disposed therebetween, and each of the non-volatile memory elements having a floating gate electrode, a control gate electrode over the floating gate electrode, and a tunnel insulation film below the floating gate electrode, the method comprising the step of: simultaneously forming the dielectric film of the capacitor element and the tunnel insulation film of the non-volatile memory element.

Claim 2

A method of manufacturing a semiconductor device having dynamic type memory elements and non-volatile memory elements on a semiconductor substrate, each of the dynamic type memory elements having a capacitance element which comprises a first electrode, a second electrode, and a dielectric film disposed therebetween, and each of the non-volatile memory elements having a floating gate electrode, a control gate electrode over the floating gate electrode, and a tunnel insulation film below the floating gate electrode, the method comprising the step of: simultaneously forming the dielectric film of the capacitor element and the tunnel insulation film of the non-volatile memory element.

Claim 19

A method of manufacturing a semiconductor device having dynamic type memory elements each comprising a series circuit of a capacitance element and a MISFET on a first region of a substrate, and non-volatile memory elements on a second region of said substrate, said method comprising the step of; (a) simultaneously forming a first electrode of said capacitance element onto said first region and a semiconductor region connected to a drain region of said non-volatile memory element onto said second region; (b) simultaneously forming a dielectric film of said capacitance element onto said first electrode in said first region and a tunnel insulation film of said non-volatile memory element onto said semiconductor region connected to a drain region in said second region; (c) simultaneously forming a second electrode of said capacitance element onto said dielectric film and a gate electrode of said MISFET in said first layer and a floating gate electrode of said non-volatile memory element onto said tunnel insulation film in said second region; (d) forming a control gate electrode of said non-volatile memory element in said second region; wherein said dynamic type memory elements each comprising said capacitance element which has said first electrode, said second electrode and said dielectric film positioned therebetween, and said MISFET having said gate electrode are formed on said first region of said substrate, and said non-volatile memory elements comprising said floating gate electrode, said control gate electrode and said tunnel insulation film positioned between said floating gate electrode and said semiconductor region are formed on said second region of said substrate.

Claim 20

A method of manufacturing a semiconductor device having dynamic type memory elements each comprising a series circuit of a capacitance element and a MISFET on a first region of a substrate, and non-volatile memory elements on a second region of said substrate, said method comprising the step of; (a) simultaneously forming a first electrode of said capacitance element onto said first region and a semiconductor region connected to a drain region of said non-volatile memory element onto said second region; (b) simultaneously forming a dielectric film of said capacitance element onto said first electrode in said first region and a tunnel insulation film of said non-volatile memory element onto said semiconductor region connected to a drain region in said second region; (c) simultaneously forming a second electrode of said capacitance element onto said dielectric film and a gate electrode of said MISFET in said first layer and a floating gate electrode of said non-volatile memory element onto said tunnel insulation film in said second region; (d) forming a control gate electrode of said non-volatile memory element in said second region; wherein said dynamic type memory elements each comprising said capacitance element which has said first electrode, said second electrode and said dielectric film positioned therebetween, and said MISFET having said gate electrode are formed on said first region of said substrate, and said non-volatile memory elements comprising said floating gate electrode, said control gate electrode and said tunnel insulation film positioned between said floating gate electrode and said semiconductor region are formed on said second region of said substrate.

Claim 25

A method of manufacturing a semiconductor device having dynamic type memory elements comprising a series circuit of a capacitance element and a MISFET on a first region of a substrate, and non-volatile memory elements on a second region of said substrate, said method comprising the steps of: (a) simultaneously forming a first electrode of said capacitance element onto said first region and a floating gate electrode of said non-volatile memory element onto said second region; (b) simultaneously forming a dielectric film of said capacitance element onto said first electrode in said first region and a gate insulation film of said non-volatile memory element onto said floating gate electrode in said second region; and (c) simultaneously forming a second electrode of said capacitance element onto said dielectric film in said first region and a control gate electrode of said non-volatile memory element onto said gate insulation film in said second region, wherein said dynamic type memory elements each comprising said capacitance element having said first electrode, said second electrode and said dielectric film positioned therebetween are formed on said first region of said substrate; and said non-volatile memory elements comprising said floating gate electrode, said control gate electrode and said gate insulation film positioned between said floating gate electrode and said control gate electrode are formed on said second region of said substrate; and wherein said dielectric film of said capacitance element is formed in a single layer of a silicon oxide film, a silicon nitride film or a tantalum oxide, or in a composite film of these films.

Claim 26

A method of manufacturing a semiconductor device having dynamic type memory elements comprising a series circuit of a capacitance element and a MISFET on a first region of a substrate, and non-volatile memory elements on a second region of said substrate, said method comprising the steps of: (a) simultaneously forming a first electrode of said capacitance element onto said first region and a floating gate electrode of said non-volatile memory element onto said second region; (b) simultaneously forming a dielectric film of said capacitance element onto said first electrode in said first region and a gate insulation film of said non-volatile memory element onto said floating gate electrode in said second region; and (c) simultaneously forming a second electrode of said capacitance element onto said dielectric film in said first region and a control gate electrode of said non-volatile memory element onto said gate insulation film in said second region, wherein said dynamic type memory elements each comprising said capacitance element having said first electrode, said second electrode and said dielectric film positioned therebetween are formed on said first region of said substrate; and said non-volatile memory elements comprising said floating gate electrode, said control gate electrode and said gate insulation film positioned between said floating gate electrode and said control gate electrode are formed on said second region of said substrate; and wherein said dielectric film of said capacitance element is formed in a single layer of a silicon oxide film, a silicon nitride film or a tantalum oxide, or in a composite film of these films.