Memory cell providing simultaneous non-destructive access to volatile and non-volatile data

Claim 2

A memory cell capable of storing separate data elements in a volatile and non-volatile portion thereof, said data elements not necessarily duplicative, having first and second input/output (I/O) bit lines and a common line held at ground potential, comprising: volatile access and storage means connected to said first I/O bit line responsive to first read and first write enable signals for receiving on said first I/O bit line signals indicative of the state of a volatile signal thereon upon reception of said first write enable signal, for storing said state of said volatile signal, and for generating on said first I/O bit line a signal indicative of the state of said stored signal upon reception of said first read enable signal; and non-volatile access and storage means connected to said second I/O bit line responsive to second read and second write enable signals for receiving on said second I/O bit line signals indicative of the state of a non-volatile signal thereon upon reception of said second write enable signal, for storing said state of said non-volatile signal, and for generating on said second I/O bit line a signal indicative of the state of said stored signal upon reception of said second read enable signal, whereby said volatile and non-volatile data elements may be non-destructively read from, or written to and stored within said volatile access and storage means, and said non-volatile access and storage means, respectively independently within a single memory cycle.

Claim 3

A memory cell according to claim 1 further including a conductive capacitor plate and a floating gate, wherein said volatile access and storage means comprises: a volatile access transistor having a first terminal connected to said first I/O bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said first read and first write enable signals during respective read and write operations; a volatile storage capacitor having a first electrode connected to said second terminal of said access transistor, and a second electrode being a first portion of said capacitor plate; and a tunneling capacitor having a first electrode connected to said first electrode of said volatile storage capacitor and a second electrode being a first portion of said floating gate.

Claim 4

A memory cell according to claim 2 wherein said terminals of said volatile access transistor and said first electrode of said volatile storage capacitors are isolated N+ regions formed along the surface of a P-monocrystalline silicon substrate.

Claim 5

A memory cell according to claim 3 wherein said second terminal of said volatile access transistor and said first electrode of said volatile storage capacitor are formed by a first isolated N+ region termed a dynamic "storage node".

Claim 6

A memory cell according to claim 4 wherein said floating gate is an isolated polysilicon layer disposed above the surface of said substrate, said second tunneling capacitor electrode forming a region on a surface of said first floating gate portion, termed a "tunneling region", disposed in close proximity to said volatile storage node which forms said first tunneling capacitor electrode.

Claim 7

A memory cell according to claim 5 further including a tunneling oxide layer disposed between said tunneling region and a surface of said volatile storage node, whereby a volatile data element may be stored by controlling the charge stored on the volatile storage capacitor.

Claim 8

A memory cell according to claim 1 further including a conductive capacitor plate, wherein said non-volatile access and storage means comprises: a non-volatile access transistor having a first terminal connected to said second I/O bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said second read and second write enable signals during respective read and write operations; a floating gate transistor having a first terminal connected to said second terminal of said access transistor, a second terminal and a gate being a portion of said floating gate; a coupling capacitor having a first electrode connected to said first terminal of said floating gate transistor and a second electrode being a second portion of said floating gate; and a non-volatile read transistor having a first terminal connected to said second terminal of said floating gate transistor, a second terminal connected to said common line, and a gate being a portion of said capacitor plate.

Claim 9

A memory cell according to claim 7 wherein said terminals of said non-volatile access and floating gate transistors are isolated N+ regions formed along the surface of a P-monocrystalline silicon substrate.

Claim 10

A memory cell according to claim 8 wherein said second terminal of said access transistor and said first terminal of said non-volatile storage transistor are formed by a first isolated N+ region termed a non-volatile "storage node".

Claim 11

A memory cell according to claim 9 wherein said floating gate is an isolated polysilicon layer disposed above the surface of said substrate, said first coupling capacitor electrode forming a region on a surface of said second floating gate portion, termed a "coupling region", disposed in close proximity to said non-volatile storage node which forms said second coupling capacitor electrode.

Claim 12

A memory cell according to claim 10 further including a tunneling oxide layer disposed between said tunneling region and a surface of said volatile storage node, whereby a non-volatile data element may be stored by the charge stored on said floating gate.

Claim 13

A memory cell according to claim 1 further including a conductive capacitor plate and a floating gate wherein said volatile access and storage means comprises: a volatile access transistor having a first terminal connected to said first I/O bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said first read and first write enable signals during respective read and write operations; a volatile storage capacitor having a first electrode connected to said second terminal of said volatile access transistor, and a second electrode being a first portion of said capacitor plate; and a tunneling capacitor having a first electrode connected to said first electrode of said volatile storage capacitor and a second electrode being a first portion of said floating gate, and wherein said non-volatile access and storage means comprises: a non-volatile access transistor having a first terminal connected to said second I/O bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said second read and second write enable signals during respective read and write operations; a floating gate transistor having a first terminal connected to said second terminal of said non-volatile access transistor, a second terminal and a gate being a portion of said floating gate; a coupling capacitor having a first electrode connected to said first terminal of said floating gate transistor and a second electrode being a second portion of said floating gate; and a non-volatile read transistor having a first terminal connected to said second terminal of said floating gate transistor, a second terminal connected to said common line, and a gate being a second portion of said capacitor plate.

Claim 14

A memory cell according to claim 12 wherein said second portion of said floating gate, which forms said first electrode of said coupling capacitor, has an area about four times that of said first portion of said floating gate, which forms said second electrode of said tunneling capacitor.

Claim 15

Memory apparatus providing access and storage of volatile and non-volatile data elements, said elements not necessarily duplicative, within a single memory cycle comprising: addressing means for generating signals on a plurality of word lines and on a plurality of bit lines and a plurality of capacitor plate (CP) lines; a plurality of memory cell means arranged into an array having rows and columns, one of said memory cell means located at the intersection of each said row with each said column, said means having a first and a second word line connected to said addressing means, a first and a second input/output (I/O) bit line and a CP line; a plurality of volatile data sensing means, one for each said row connected to said first I/O bit line; a plurality of non-volatile sensing means, one for each said row connected to said second I/O bit line; and a plurality of comparator means, one for each said row connected to said non-volatile sensing means and said volatile sensing means in said row.

Claim 16

Memory apparatus providing access and storage of volatile and non-volatile data elements, said elements not necessarily duplicative, within a single memory cycle comprising: addressing means for generating signals on a plurality of word lines and on a plurality of bit lines and a plurality of capacitor plate (CP) lines; a plurality of memory cell means arranged into an array having rows and columns, one of said memory cell means located at the intersection of each said row with each said column, said means having a first and a second word line connected to said addressing means, a first and a second input/output (I/O) bit line and a CP line; a plurality of volatile data sensing means, one for each said row connected to said first I/O bit line; a plurality of non-volatile sensing means, one for each said row connected to said second I/O bit line; and a plurality of comparator means, one for each said row connected to said non-volatile sensing means and said volatile sensing means in said row.

Claim 17

A memory cell capable of independently storing data in a volatile and a non-volatile portion thereof, said data not necessarily duplicative, having a first and a second input/output (I/O) bit line and a common line held at ground potential, comprising: a floating gate having at least first and second planar portions; a tunneling capacitor having a first and a second electrode which forms said first floating gate portion; a first semiconductor device for storing a quantum of charge indicative of said volatile data state; a coupling capacitor having a first electrode which forms said second floating gate portion and a second electrode; a second semiconductor device for storing a quantum of charge indicative of said non-volatile data state; means responsive to first read and first write enable signals during respective read and write operations for transferring volatile data between said first input/output (I/O) bit line and said tunneling capacitor; and means responsive to second read and second write enable signals during respective read and write operations for transferring non-volatile data between said second input/output (I/O) bit line and said coupling capacitor; whereby volatile and non-volatile data elements may be independently read from, or written to and stored within, said first semiconductor device and said second semiconductor device, respectively, within a single memory cycle.

Claim 18

A memory cell capable of independently storing data in a volatile and a non-volatile portion thereof, said data not necessarily duplicative, having a first and a second input/output (I/O) bit line and a common line held at ground potential, comprising: a floating gate having at least first and second planar portions; a tunneling capacitor having a first and a second electrode which forms said first floating gate portion; a first semiconductor device for storing a quantum of charge indicative of said volatile data state; a coupling capacitor having a first electrode which forms said second floating gate portion and a second electrode; a second semiconductor device for storing a quantum of charge indicative of said non-volatile data state; means responsive to first read and first write enable signals during respective read and write operations for transferring volatile data between said first input/output (I/O) bit line and said tunneling capacitor; and means responsive to second read and second write enable signals during respective read and write operations for transferring non-volatile data between said second input/output (I/O) bit line and said coupling capacitor; whereby volatile and non-volatile data elements may be independently read from, or written to and stored within, said first semiconductor device and said second semiconductor device, respectively, within a single memory cycle.

Claim 19

A memory cell according to claim 15 further including a conductive capacitor plate, wherein said volatile data transfer means comprises: a volatile access transistor having a first terminal connected to said first input/output (I/O) bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said first read and first write signals during respective read and write operations; and a tunneling structure for charging and discharging said first floating gate portion; and wherein said first semiconductor device comprises a volatile storage capacitor having a first electrode connected to said second terminal of said volatile access transistor, and a second electrode being a first portion of said capacitor plate; said second electrode of said volatile storage capacitor and said floating gate first portion forming said tunneling capacitor; whereupon reception of said first write enable signal causes said volatile access transistor to become conducting and said volatile storage capacitor and said volatile access transistor to tunnel electrons between said floating gate first portion and said first terminal of said volatile access transistor to adjust the quantum of charge stored on said first floating gate portion to correspond to the data on said first input/output (I/O) bit line.

Claim 20

A memory cell according to claim 16 wherein said non-volatile data transfer means comprises: a non-volatile access transistor having a first terminal connected to said second input/output (I/O) bit line, a second terminal, and having an access control gate for coupling said first terminal to said second terminal responsive to said second read and second write signals during respective read and write operations; and a coupling structure for charging and discharging said second floating gate portion; wherein said second semiconductor comprises a floating gate transistor having a first terminal connected to said second terminal of said static access transistor, a second terminal and a gate being a portion of said floating gate; said second terminal of said floating gate transistor and said floating gate second portion forming said coupling capacitor; whereupon receiption of said second write enable signal causes said floating gate transistor and said non-volatile access transistor to tunnel electrons between said floating gate second portion and said first terminal of said non-volatile access transistor to adjust the quantum of charge stored on said second floating gate portion to correspond to data on said second input/output (I/O) bit line.

Claim 21

A memory cell according to claim 17 wherein said second terminal of said volatile access transistor and said first electrode of said volatile storage capacitor are formed by a first isolated N+ region, termed a "volatile storage node" and wherein said first terminal of said non-volatile access transistor and said second terminal of said floating gate transistor are formed by a second isolated N+ region, termed a "non-volatile storage node", and wherein said tunneling structure includes a tunneling region on a surface of said floating gate corresponding to said first portion thereof disposed over said volatile storage node for charging and discharging said floating gate first portion, and said tunneling structure includes a coupling region on a surface of said floating gate corresponding to said second portion thereof disposed over said non-volatile storage node for coupling said floating gate second portion, whereupon reception of said second write enable signal causes said volatile and non-volatile access transistors to become conducting and causing electrons to tunnel between said floating gate and said second terminal of said volatile access transistor to adjust the quantum of charge stored on said floating gate first and said second portion to correspond to the data on said second input/output (I/O) bit line.

Claim 22

A memory cell according to claim 18 wherein said second floating gate portion has an area about four times that of said first floating gate portion, whereby, upon application of a voltage on said second input/output (I/O) bit line, said floating gate will be at a voltage closer to that of said non-volatile storage node than to that of said volatile storage node.

Claim 25

The volatile and non-volatile accessing method according to claim 20 further including a method of storing a volatile data element comprising the steps of: (g) initializing the voltage level on said volatile storage node, V ST ; (h) applying on said capacitor plate a voltage equal to said third value; (i) applying on said first word line a voltage level equal to said fourth value; and (j) applying on said first input/output (I/O) bit line a voltage indicative of the state of said volatile data element to be stored.

Claim 26

The volatile and non-volatile accessing method according to claim 20 further including a method of storing a non-volatile data element comprising the steps of: (k) initializing the voltage level on said floating gate, V FG ; (l) applying on said capacitor plate a voltage level equal to said third value; (m) applying on said first and said second word lines a voltage level equal to a fourth value; and (n) applying on said first input/output (I/O) bit line a voltage level equal to a sixth value and to said second input/output (I/O) bit line a voltage level equal to said third value indicative of said non-volatile data element being of a first state or applying on said first I/O bit line a voltage level equal to said third value and to said second I/O bit line a voltage level equal to said sixth value indicative of said non-volatile data element being of a second state.