MOS Voltage divider structure suitable for higher potential feedback regulation

Claim 2

In a metal-oxide-semiconductor integrated circuit formed on a silicon substrate, a voltage divider comprising: a first and a second polysilicon member each insulated from said substrate and from each other; a third and a fourth polysilicon member each insulated from each other and from said first and second polysilicon members; said third polysilicon member being disposed over a portion of said first and second polysilicon members so as to provide capacitance between said third polysilicon member and said first and second polysilicon members, said third polysilicon member being completely surrounded by insulation; said fourth polysilicon member being disposed above said second polysilicon member so as to provide capacitance between said second and fourth polysilicon members; said first, second and fourth members being coupled to terminals for said divider; whereby said circuit provides a voltage divider between said first and second members.

Claim 3

The voltage divider defined by claim 1 wherein said first and second members are fabricated from a first layer of polysilicon and wherein said third and fourth members are fabricated from a second layer of polysilicon.

Claim 4

The voltage divider defined by claim 2 wherein said first and second polysilicon members are insulated from third and fourth polsilicon members by a layer of silicon dioxide grown from said first layer of polysilicon.

Claim 5

In a metal-oxide-semiconductor integrated circuit formed on a silicon substrate, a voltage divider comprising: a first and a second polysilicon member insulated from one another forming a first capacitor; a third and a fourth polysilicon member insulated from one another forming a second capacitor, said first and second capacitors being spaced-apart from one another, said first and third polysilicon members being formed from a first layer of polysilicon and said second and fourth polysilicon members being formed from a second layer of polysilicon; a fifth polysilicon member disposed generally between said first and second capacitors and formed from said first layer of polysilicon; a sixth and seventh polysilicon member formed from said second layer of polysilicon and disposed over said fifth polysilicon member, said sixth polysilicon member being connected to said second polysilicon member and said seventh polysilicon member being connected to said fourth polysilicon member; and a plurality of eighth polysilicon members formed from said second layer of polysilicon and disposed generally over said fifth polysilicon member, whereby a voltage divider is realized.

Claim 6

In a metal-oxide-semiconductor integrated circuit formed on a silicon substrate, a voltage divider comprising: a first and a second polysilicon member insulated from one another forming a first capacitor; a third and a fourth polysilicon member insulated from one another forming a second capacitor, said first and second capacitors being spaced-apart from one another, said first and third polysilicon members being formed from a first layer of polysilicon and said second and fourth polysilicon members being formed from a second layer of polysilicon; a fifth polysilicon member disposed generally between said first and second capacitors and formed from said first layer of polysilicon; a sixth and seventh polysilicon member formed from said second layer of polysilicon and disposed over said fifth polysilicon member, said sixth polysilicon member being connected to said second polysilicon member and said seventh polysilicon member being connected to said fourth polysilicon member; and a plurality of eighth polysilicon members formed from said second layer of polysilicon and disposed generally over said fifth polysilicon member, whereby a voltage divider is realized.

Claim 7

The voltage divider defined by claim 4 wherein said first layer and second layer of polysilicon are separated by an oxide layer.

Claim 8

The voltage divider defined by claim 5 wherein said polysilicon members formed from said second layer of polysilicon lie within the outline of said polysilicon members formed from said first layer of polysilicon, thereby compensating for masking misalignments.

Claim 9

The voltage divider defined by claim 5 wherein the capacitors formed by said polysilicon members fabricated from said first layer of polysilicon and said polysilicon members fabricated from said second layer of polysilicon are dispersed so as to compensate for variations in thickness of said oxide layer.

Claim 10

The voltage divider defined by claim 7 wherein said fifth polysilicon member is a generally square member with opposite corners removed and wherein said first and second capacitors are formed within said opposite corners.

Claim 11

The voltage divider defined by claim 8 wherein said second, fourth, sixth, seventh and plurality of eighth polysilicon members each have approximately equal area.

Claim 12

The voltage divider defined by claim 9 wherein an input signal to said voltage divider is applied between said first and third polysilicon members and an output signal from said voltage divider is taken from said fifth polysilicon members.