Means for coupling incompatible signals to an integrated circuit and for deriving operating supply therefrom

Claim 2

A semiconductor structure including a 3 plate capacitor comprising: (a) a lower relatively conductive region of heavily doped silicon, (b) a first insulating layer covering the conductive region, (c) a first polycrystalline relatively conductive layer disposed over the first insulating layer covering at least a substantial portion of the bottom conductive region, (d) a second insulating layer covering the polycrystalline layer, (e) an upper conductive layer disposed over the second insulating layer, and (f) conductive means contacting said polycrystalline layer for providing an output signal upon an input signal being a.c. coupled between the upper conductive layer and lower conductive region.

Claim 3

A semiconductor structure as defined in claims 1 in which the lower conductive region is a heavily doped P+ or N+ region in the surface of a silicon wafer.

Claim 4

A semiconductor structure as defined in claim 1 in which the lower conductive region is a heavily doped P+ or N+ region in the surface of an epitaxial layer carried by a silicon wafer.

Claim 5

A semiconductor structure as defined in claim 2, in which the material of the upper conductive layer is polycrystalline silicon.

Claim 6

A semiconductor structure as defined in claim 2 in which the material of the upper conductive layer is aluminum.

Claim 7

A semiconductor structure as defined in claim 2 in which the upper conductive layer is at least part of a contact pad for a wire bond.

Claim 8

A semiconductor structure as defined in claim 4 or 5 further comprising at least one voltage reference diode connected between said first polycrystalline layer and a source of reference potential.

Claim 9

A semiconductor structure as defined in claim 4 or 5 further comprising a zener diode connected in a series circuit between said first polycrystalline layer and a source of reference potential.

Claim 10

A semiconductor structure as defined in claim 4 or 5 further including a plurality of MOS transistors each having its gate short circuited to its drain, connected in series between the first polycrystalline layer and a source of reference potential.

Claim 11

A semiconductor structure as defined in claim 4 or 5 further including a plurality of MOS transistors each having its gate short circuited to its drain, connected in series between the first polycrystalline layer and the silicon wafer ground.

Claim 12

A semiconductor structure as defined in claim 4 or 5 further including a plurality of MOS transistors each having its gate short circuited to its drain, connected in series between the first polycrystalline layer and the lower conductive region of heavily doped silicon.

Claim 13

A semiconductor structure as defined in claim 4 or 5 further including a plurality of MOS transistors each having its gate short circuited to its drain, connected in series between the first polycrystalline layer and the silicon wafer ground, and means for connecting one terminal of a source of signal to the upper conductive layer, and for AC coupling the other terminal of the source of power to said lower conductive region.

Claim 14

A semiconductor structure as defined in claim 4 or 5 further including a plurality of MOS transistor each having its gate short circuited to its drain, connected in series between the first polycrystalline layer and the silicon wafer ground, and means for connecting one terminal of a source of clock signals to the upper conductive layer, and for AC coupling the other terminal of the source of clock signals to said lower conductive region.

Claim 15

A semiconductor integrated circuit structure comprising: (a) a plurality of interconnected CMOS transistors, (b) a power input bus to said transistors, (c) an input terminal for clock signals connected to predetermined ones of said transistors, (d) a pair of series connected capacitor means, one capacitor means having a bottom conductive region of heavily doped silicon, a first silicon dioxide insulating layer covering the conductive region, and an upper conductive layer over the insulating layer covering at least a substantial portion of the bottom conductive region, (e) the junction between the pair of capacitor means being connected through circuit means to the power input bus, (f) the input terminal for clock signals being connected to the other terminal of the other of the pair of capacitor means, whereby the clock source provides both clock signals and operating power for said transistors.

Claim 16

A semiconductor integrated circuit structure comprising: (a) a plurality of interconnected CMOS transistors, (b) a power input bus to said transistors, (c) an input terminal for clock signals connected to predetermined ones of said transistors, (d) a pair of series connected capacitor means, one capacitor means having a bottom conductive region of heavily doped silicon, a first silicon dioxide insulating layer covering the conductive region, and an upper conductive layer over the insulating layer covering at least a substantial portion of the bottom conductive region, (e) the junction between the pair of capacitor means being connected through circuit means to the power input bus, (f) the input terminal for clock signals being connected to the other terminal of the other of the pair of capacitor means, whereby the clock source provides both clock signals and operating power for said transistors.

Claim 17

A semiconductor integrated circuit structure as defined in claim 14, in which the circuit means is comprised of a plurality of series connected MOS transistors each having its gate short circuited to its drain, connected between the junction of said capacitor means and a source of reference potential.

Claim 18

A semiconductor integrated circuit structure as defined in claim 15, in which the source of reference potential is the integrated circuit substrate.

Claim 19

A semiconductor integrated circuit structure as defined in claim 14, 15 or 16, in which the circuit means is comprised of a rectifier connected between the junction of the pair of capacitor means and the power input bus.

Claim 20

A semiconductor integrated circuit as defined in claim 14, 15 or 16, in which said upper conductive layer and the pair of capacitor means is fabricated of polycrystalline silicon, and further comprising a second silicon dioxide insulating layer covering said upper conductive layer, and a top conductive layer disposed over the second insulating layer covering at least a substantial portion of the upper conductive layer.

Claim 21

A semiconductor integrated circuit as defined in claim 14, 15 or 16, in which said upper conductive layer of the pair of capacitor means is fabricated of polycrystalline silicon, and further comprising a second silicon dioxide insulating layer covering at least a substantial portion of the upper conductive layer, and a top conductive capacitor plate comprising at least a portion of a wire bonding pad disposed over the second insulating layer.