US3789246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Insulated dual gate field-effect transistor signal translator having means for reducing its sensitivity to supply voltage variations
Assignee: RCA Corp
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Filing: 1972-02-14
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Granted: 1974-01-29
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Expires: 1992-02-14
Abstract
Abstract An oscillator circuit is described using a dual gate MOS-FET transistor. Drift of the oscillating frequency of the oscillator circuit caused by drain supply voltage variations is minimized by suitable bias voltages applied to the two gates. The gate bias voltages are derived from the same principle supply, but the gate voltage variations must be nonlinear with respect to the drain voltage variations to achieve frequency stability. The suitable gate voltages are achieved by means of a voltage divider composed of dual gate MOS-FET transistors.
Inventors
- 👤 J Preisig
- 👤 A Presser
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:08
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/02; H03B5/04
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
258 words
In a circuit of the type including a plural gate, field effect transistor having a source electrode, a drain electrode and at least two gate electrodes formed on a substrate of semiconductor material with the gate electrodes insulated from said substrate and from the drain and source electrodes, means for connecting a power supply the output of which may vary between said source and drain electrodes for biasing said transistor, the operating characteristics of said circuit changing with said power supply output variations, the improvement comprising: a bias control means including a voltage divider circuit having a first portion and a second portion joined to each other, said first portion containing at least one field effect transistor having source, drain and gate electrodes and characterized by only the gate and drain electrodes connected to each other, said second portion containing at least one insulated gate field effect transistor having source, drain and gate electrodes and characterized by at least one of its gate electrodes connected to its source electrode, and means connecting one of said gate electrodes of said plural gate, field effect transistor to the junction of said portions and for connecting said power supply connecting means to a point near one end of said voltage divider circuit, said bias control means responsive to said power supply output variations for providing at said one gate electrode of said plural gate, field effect transistor a bias which substantially offsets the effect of said power supply output variations in a manner to minimize said changes in said operating characteristics.
Claim 2
Dependent Claim
258 words
In a circuit of the type including a plural gate, field effect transistor having a source electrode, a drain electrode and at least two gate electrodes formed on a substrate of semiconductor material with the gate electrodes insulated from said substrate and from the drain and source electrodes, means for connecting a power supply the output of which may vary between said source and drain electrodes for biasing said transistor, the operating characteristics of said circuit changing with said power supply output variations, the improvement comprising: a bias control means including a voltage divider circuit having a first portion and a second portion joined to each other, said first portion containing at least one field effect transistor having source, drain and gate electrodes and characterized by only the gate and drain electrodes connected to each other, said second portion containing at least one insulated gate field effect transistor having source, drain and gate electrodes and characterized by at least one of its gate electrodes connected to its source electrode, and means connecting one of said gate electrodes of said plural gate, field effect transistor to the junction of said portions and for connecting said power supply connecting means to a point near one end of said voltage divider circuit, said bias control means responsive to said power supply output variations for providing at said one gate electrode of said plural gate, field effect transistor a bias which substantially offsets the effect of said power supply output variations in a manner to minimize said changes in said operating characteristics.
Claim 3
Dependent Claim
72 words
The circuit claimed in claim 1 wherein said first portion includes at least one voltage dividing dual insulated gate field effect transistor having both of its gate electrodes connected to its drain electrode and said second portion includes at least one voltage dividing dual insulated gate field effect transistor having one of its gate electrodes connected to its source electrode and the other of its gate electrodes connected to its drain electrode.
Claim 4
Dependent Claim
75 words
The circuit claimed in claim 2 wherein said first portion is made up of six serially connected identical dual gate, field effect transistors each having both gate electrodes connected to its drain electrode and said second portion is made up of two parallel connected dual insulated gate, field effect transistors each having a first of its gate electrodes connected to its source electrOde and the second of its gate electrodes connected to its drain electrode.
Claim 5
Dependent Claim
73 words
The circuit claimed in claim 2 wherein said bias control means further includes a second voltage divider coupled between the junction of said first and second portions and said source electrode of said first-mentioned dual gate field effect transistor, said second divider including at least two series connected dual gate field effect transistors the junction of which is coupled to the other of said gate electrodes of said plural gate, field effect transistor.
Claim 6
Dependent Claim
33 words
The invention claimed in claim 4 wherein said second divider is made up of two dual gate field effect transistors with both gate electrodes of each transistor connected to the drain electrode thereof.
Claim 7
Dependent Claim
87 words
The circuit claimed in claim 2 wherein said second portion is made up of a single dual gate field effect transistor having a given channel width and having one of its gate electrodes connected to its source electrode and the other of its gate electrodes connected to its drain electrode and wherein said first portion is made up of a single dual gate field effect transistor having a channel width 1/12th said given channel width and having both of its gate electrodes connected to its drain electrode.
Claim 8
Dependent Claim
126 words
A voltage divider for developing a voltage which can be used to offset variations in the output of a direct current power supply, comprising: a first portion including at least one dual gate field effect transistor having its two gate electrodes connected to the drain electrode thereof, a second portion including at least one dual gate field effect transistor having one gate electrode connected to the drain electrode and the other gate electrode connected to the source electrode thereof, means for connecting said first and second portions in series between the terminals of said power supply, the operating characteristics of said first and second transistors being determined to cause a voltage to appear at the junction of said portions reflecting said variations in a compensating manner.
Claim 9
Dependent Claim
126 words
A voltage divider for developing a voltage which can be used to offset variations in the output of a direct current power supply, comprising: a first portion including at least one dual gate field effect transistor having its two gate electrodes connected to the drain electrode thereof, a second portion including at least one dual gate field effect transistor having one gate electrode connected to the drain electrode and the other gate electrode connected to the source electrode thereof, means for connecting said first and second portions in series between the terminals of said power supply, the operating characteristics of said first and second transistors being determined to cause a voltage to appear at the junction of said portions reflecting said variations in a compensating manner.
Claim 10
Dependent Claim
58 words
A voltage divider as claimed in claim 7 means connecting the drain of said first-mentioned transistor to one terminal of said power supply and the source of said second-mentioned transistor to a return terminal of said power supply, and means to connect the source of said first-mentioned transistor to the drain of said second-mentioned transistor at said junction.
Claim 11
Dependent Claim
105 words
A voltage divider as claimed in claim 8, said first portion including a plurality of similar dual gate field effect transistors series connected drain-to-source with the drain of the transistor at one end of said series connected to said one power supply terminal and the source of the transistor at the other end of the said series connected to said junction, said second portion including a plurality of dual gate field effect transistors parallel connected drain-to-drain and source-to-source will all the drains of said parallel transistors connected to said junction and all the sources of said parallel transistors connected to said power supply return terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-28 | 1977-07-30 | 1978-01-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-28 | 1981-07-30 | 1982-01-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-28 | 1985-07-30 | 1986-01-29 | $7700.00 | Window Closed / Lapsed |