US5547880A
Expired / Lapsed
US
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Method for forming a zener diode region and an isolation region
Assignee: Vishay Siliconix Inc
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Filing: 1995-06-05
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Granted: 1996-08-20
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Expires: 2015-06-05
Abstract
Abstract A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.
Inventors
- 👤 Richard K. Williams
- 👤 Hamza Yilmaz
- 👤 Michael E. Cornell
- 👤 Jun W. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D30/601; H10D30/603; H10D30/66; H10D30/663; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/403; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/126; Y10S438/00; Y10S438/983
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
153 words
A method for forming a zener diode region and an isolation region comprising the steps of: forming an isolation region of a first conductivity type extending from a first surface area of an epitaxial layer of a second conductivity type and contacting a semiconductor material of said first conductivity type located below said first surface area, said isolation region having a first impurity concentration; and implanting ions of said first conductivity type into a second surface area of said epitaxial layer, after said step of forming an isolation region, to form a zener diode region of said first conductivity type in said second surface area for use in forming a zener diode having a selected reverse breakdown voltage, said zener diode region having a second impurity concentration higher than said first impurity concentration, said step of implanting also including implanting said ions in said first surface area to additionally dope said isolation region.
Claim 2
Independent Claim
153 words
A method for forming a zener diode region and an isolation region comprising the steps of: forming an isolation region of a first conductivity type extending from a first surface area of an epitaxial layer of a second conductivity type and contacting a semiconductor material of said first conductivity type located below said first surface area, said isolation region having a first impurity concentration; and implanting ions of said first conductivity type into a second surface area of said epitaxial layer, after said step of forming an isolation region, to form a zener diode region of said first conductivity type in said second surface area for use in forming a zener diode having a selected reverse breakdown voltage, said zener diode region having a second impurity concentration higher than said first impurity concentration, said step of implanting also including implanting said ions in said first surface area to additionally dope said isolation region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |