US4887142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Monolithically integrated semiconductor device containing bipolar junction transistors, CMOS and DMOS transistors and low leakage diodes and a method for its fabrication
Assignee: STMicroelectronics SRL
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Filing: 1988-11-28
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Granted: 1989-12-12
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Expires: 2008-11-28
Abstract
Abstract Disclosed is a monolithic integrated semiconductor device which may contain specimens of seven different circuit components; namely: lateral N-MOS and lateral P-MOS transistors (CMOS), vertical N-DMOS and vertical P-DMOS transistors, vertical NPN bipolar transistors, vertical PNP bipolar transistors with isolated collector and low leakage junction diodes as well as a process for fabricating such a device.
Inventors
- 👤 Franco Bertotti
- 👤 Carlo Cini
- 👤 Claudio Contiero
- 👤 Paola Galbiati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
61 words
An integrated semiconductor circuit formed on a single monolithic substrate of semiconductor material comprising: a pair of vertical complementary DMOS transistors; a CMOS transistor structure; a vertical PNP bipolar junction transistor with isolated collector; a vertical NPN bipolar junction transistor; and a low leakage integrated diode having a heavily doped surrounding wall region contacting a second heavliy doped bottom anode region.
Claim 2
Dependent Claim
61 words
An integrated semiconductor circuit formed on a single monolithic substrate of semiconductor material comprising: a pair of vertical complementary DMOS transistors; a CMOS transistor structure; a vertical PNP bipolar junction transistor with isolated collector; a vertical NPN bipolar junction transistor; and a low leakage integrated diode having a heavily doped surrounding wall region contacting a second heavliy doped bottom anode region.
References Cited (Backward Citations)
US4546370A
Cited
US4589004A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-11 | 1993-06-12 | 1993-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-11 | 1997-06-12 | 1997-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-11 | 2001-06-12 | 2001-12-12 | $7700.00 | Window Closed / Lapsed |