US4546370A
Expired / Lapsed
US
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Monolithic integration of logic, control and high voltage interface circuitry
Assignee: Texas Instruments Inc
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Filing: 1984-11-21
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Granted: 1985-10-08
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Expires: 2004-11-21
Abstract
Abstract Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.
Inventors
- 👤 Patrick A. Curran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:16
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01825; H03K19/01831; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
117 words
An integrated semiconductor circuit, comprising: a self-aligned D-MOS transistor, having a channel region, a source and a drain on opposite sides of said channel region, and a backgate region at least partially within said channel region; and a vertical NPN transistor, having an emitter, a base and a collector, said NPN transistor being isolated from said D-MOS transistor to enable high performance operation thereof; the D-MOS transistor having a diffused dopant concentration profile in said channel region; the emitter of said NPN transistor being formed in a well having a diffused dopant concentration profile corresponding to said dopant concentration profile of said D-MOS transistor channel region; whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
Claim 2
Dependent Claim
117 words
An integrated semiconductor circuit, comprising: a self-aligned D-MOS transistor, having a channel region, a source and a drain on opposite sides of said channel region, and a backgate region at least partially within said channel region; and a vertical NPN transistor, having an emitter, a base and a collector, said NPN transistor being isolated from said D-MOS transistor to enable high performance operation thereof; the D-MOS transistor having a diffused dopant concentration profile in said channel region; the emitter of said NPN transistor being formed in a well having a diffused dopant concentration profile corresponding to said dopant concentration profile of said D-MOS transistor channel region; whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
Claim 3
Dependent Claim
23 words
The integrated semiconductor circuit of claim 1 further comprising a monocrystalline p-type semiconductor substrate upon which said D-MOS and NPN transistors are formed.
Claim 4
Dependent Claim
59 words
The integrated semiconductor circuit of claim 2 further comprising a plurality of isolated regions of n-type material formed upon said substrate; and a plurality of wells of lightly doped p-type material, formed in respective ones of said regions of said n-type material in which said channel of said D-MOS transistor and said emitter of said NPN transistor are formed.
Claim 5
Dependent Claim
23 words
The integrated semiconductor circuit of claim 3 wherein said dopant is boron ions having a surface concentration of 1×10 17 /cm 3 .
Claim 6
Dependent Claim
193 words
An integrated semiconductor circuit, comprising: a monocrystalline p-type semiconductor substrate; a plurality of regions of n-type semiconductor formed upon said substrate, said regions being isolated from each other to enable high performance operation of transistor devices formed therein; a plurality of wells of lightly doped p-type material selectively formed within said n-type semiconductor regions; a self-aligned D-MOS transistor, in one of said regions, and having a channel formed in one of said wells, a source and a drain on opposite sides of said channel, and a backgate adjacent said channel away from said source and drain; and a vertical NPN transistor, in another of said n-type semiconductor regions, and having an emitter, a base and a collector, said base being formed in another one of said wells; the well in which said channel of said D-MOS transistor is formed having a diffused dopant concentration profile; the well in which the emitter of said NPN transistor is formed having a diffused dopant concentration profile corresponding to said dopant concentration profile of said well in which said channel of said D-MOS transistor is formed; whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
Claim 7
Dependent Claim
193 words
An integrated semiconductor circuit, comprising: a monocrystalline p-type semiconductor substrate; a plurality of regions of n-type semiconductor formed upon said substrate, said regions being isolated from each other to enable high performance operation of transistor devices formed therein; a plurality of wells of lightly doped p-type material selectively formed within said n-type semiconductor regions; a self-aligned D-MOS transistor, in one of said regions, and having a channel formed in one of said wells, a source and a drain on opposite sides of said channel, and a backgate adjacent said channel away from said source and drain; and a vertical NPN transistor, in another of said n-type semiconductor regions, and having an emitter, a base and a collector, said base being formed in another one of said wells; the well in which said channel of said D-MOS transistor is formed having a diffused dopant concentration profile; the well in which the emitter of said NPN transistor is formed having a diffused dopant concentration profile corresponding to said dopant concentration profile of said well in which said channel of said D-MOS transistor is formed; whereby said dopant concentration profiles determine the D-MOS transistor threshold voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |