← Back to Patent Explorer
US5262345A Expired / Lapsed US ⏱️ 0.0 years remaining

Complimentary bipolar/CMOS fabrication method

Assignee: Analog Devices Inc
•
Filing: 1992-05-15
•
Granted: 1993-11-16
•
Expires: 2012-05-15
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A complementary bipolar process enables both PNP and NPN transistors to be added to a CMOS process with a minimum of extra fabrication steps. The P-well of a CMOS process is used for the collector region of the PNP transistor and the "down isolation" for the NPN transistor. A buried P diffusion provides "up" isolation for the NPN transistor and buried collector for the PNP transistor. A method for increasing the NPN buried collector to "up" isolation breakdown voltage is described which uses multiple N type impurities.

Inventors

  • 👤 Mohammad S. Nasser
  • 👤 Saurabh M. Desai
  • 👤 Derek F. Bowers

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 00:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D10/00; H10D10/40; H10D10/421; H10D10/60; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01; Y; Y10; Y10S; Y10S148/00; Y10S148/009

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 172 words
A method of forming complementary PNP and NPN bipolar transistors simultaneously with complementary P-channel and N-channel metal oxide semiconductor (CMOS) transistors on a common substrate with an N-type epitaxial layer, comprising: forming a first P-well for an N-channel MOS transistor, a second P-well for an NPN bipolar transistor and a collector well for a PNP bipolar transistor layer by a common diffusion of P-type dopant into said epitaxial layer, forming an N-base and a P-emitter within said collector well for the PNP bipolar transistor, forming a source and drain for said P-channel MOS transistor within said epitaxial layer in a common diffusion of P-type dopant with the emitter of said PNP bipolar transistor, forming a P-base, N-emitter and N-collector within said second P-well for said NPN bipolar transistor, said second P-well isolating said NPN bipolar transistor from other devices on said substrate, and forming a source and drain within said first P-well for said N-channel MOS transistor in a common diffusion of N-type dopant with the emitter of said NPN bipolar transistor.
Claim 2
Independent Claim 172 words
A method of forming complementary PNP and NPN bipolar transistors simultaneously with complementary P-channel and N-channel metal oxide semiconductor (CMOS) transistors on a common substrate with an N-type epitaxial layer, comprising: forming a first P-well for an N-channel MOS transistor, a second P-well for an NPN bipolar transistor and a collector well for a PNP bipolar transistor layer by a common diffusion of P-type dopant into said epitaxial layer, forming an N-base and a P-emitter within said collector well for the PNP bipolar transistor, forming a source and drain for said P-channel MOS transistor within said epitaxial layer in a common diffusion of P-type dopant with the emitter of said PNP bipolar transistor, forming a P-base, N-emitter and N-collector within said second P-well for said NPN bipolar transistor, said second P-well isolating said NPN bipolar transistor from other devices on said substrate, and forming a source and drain within said first P-well for said N-channel MOS transistor in a common diffusion of N-type dopant with the emitter of said NPN bipolar transistor.
Claim 3
Dependent Claim 37 words
The method of claim 1, wherein a P-type isolation barrier is formed in the epitaxial layer around the NPN bipolar transistor in a diffusion of P-type dopant which is common with said P-well and collector well diffusion.
Claim 4
Dependent Claim 47 words
The method of claim 1, wherein a guard ring for the N-channel MOS transistor and the base of the NPN bipolar transistor are formed by a common diffusion of P-type dopant; and the emitter of the NPN bipolar transistor is formed within the base of that transistor.
Claim 5
Dependent Claim 25 words
The method of claim 1, wherein the dopant concentration in the P-well and collector well are not more than about 10 16 ions/cm 3 .

References Cited (Backward Citations)

US4637125A Cited
US4721684A Cited
US4927776A Cited
US4954456A Cited
US5001076A Cited
US5001073A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-11-15 1997-05-17 1997-11-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-11-15 2001-05-17 2001-11-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-11-15 2005-05-17 2005-11-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag