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US4826780A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making bipolar transistors

Assignee: Panasonic Holdings Corp
•
Filing: 1987-11-23
•
Granted: 1989-05-02
•
Expires: 2007-11-23
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Abstract

Abstract In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p - -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p - -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p - -regions (40) and (49) are formed simultaneously with the p - -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p - -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.

Inventors

  • 👤 Toyoki Takemoto
  • 👤 Tadao Komeda
  • 👤 Haruyasu Yamada
  • 👤 Tsutomu Fujita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 06:15
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D84/658; H10D84/01; H10D84/0112; H10D84/0119; H10D84/0121; H10D84/02; H10D84/03; H10D84/038; H10D84/40; H10D84/401; H10D84/67; H10D84/673; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30; H10W15/00; H10W15/01; H10D84/83138; H10D84/8314; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/151

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 170 words
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; forming a sixth region of an n-type in said fourth region from a upper surface of said fourth region; simultaneously forming seventh, eight and ninth regions of p-type in said sixth, fifth and third regions respectively from upper surfaces of said sixth, fifth and third regions; and simultaneously forming tenth and eleventh regions of n-type in said sixth and ninth regions from upper surfaces of said sixth and ninth regions, respectively, whereby said fourth, sixth and seventh regions form a pnp type vertical bipolar transistor, and said fifth and eight regions from a resistance device, and said third, ninth and eleventh regions forming an npn type vertical bipolar transistor.
Claim 2
Independent Claim 170 words
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; forming a sixth region of an n-type in said fourth region from a upper surface of said fourth region; simultaneously forming seventh, eight and ninth regions of p-type in said sixth, fifth and third regions respectively from upper surfaces of said sixth, fifth and third regions; and simultaneously forming tenth and eleventh regions of n-type in said sixth and ninth regions from upper surfaces of said sixth and ninth regions, respectively, whereby said fourth, sixth and seventh regions form a pnp type vertical bipolar transistor, and said fifth and eight regions from a resistance device, and said third, ninth and eleventh regions forming an npn type vertical bipolar transistor.
Claim 3
Dependent Claim 60 words
A method as in claim 1, comprising the further steps of: forming a twelfth region of n-type at a border area of said first region and said semiconductor substrate; and forming a thirteenth region of n-type in said first region from said upper surface of said first region in such a manner that said thirteenth region reaches said twelfth region.
Claim 4
Dependent Claim 20 words
A method as in claim 2, comprising the further step of electrically connecting said sixth region to said thirteenth region.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-05-01 1992-10-31 1993-05-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-05-01 1996-10-31 1997-05-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-05-01 2000-10-31 2001-05-02 $7700.00 Window Closed / Lapsed

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