US4510676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a lateral PNP transistor
Assignee: International Business Machines Corp
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Filing: 1983-12-06
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Granted: 1985-04-16
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Expires: 2003-12-06
Abstract
Abstract A method for making a lateral PNP transistor simultaneously with an NPN transistor and the resultant device wherein a first mask defines a base-width by the resistor implant for a P-type resistor and a second mask is overlaid asymmetrically on said first mask to partially cover the collector. At the same time that the NPN extrinsic base contact is made, P-type dopants are introduced in the areas exposed by the first and second masks to provide an emitter and a collector contact for the PNP transistor.
Inventors
- 👤 Narasipur G. Anantha
- 👤 Santosh P. Gaur
- 👤 Yi-Shiou Huang
- 👤 Paul J. Tsang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:59
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/061; H10D10/60; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D62/138; H10D84/00; H10D84/01; H10D84/0112; H10D84/0114; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
209 words
A method for making an asymmetrical lateral PNP transistor having a graded collector junction simultaneously with the process steps for making NPN transistors and P-type resistors, comprising the steps of: forming a semiconducting region into which said PNP and NPN transistors and said resistors are to be formed, by forming said semiconducting region containing isolated N + regions and overlying N - regions; forming at least one P - region, simultaneously with forming said resistors, one of said P - layers being adjacent a portion of one of said N - regions to define a collector-base junction of said PNP transistor; forming a first P + region, simultaneously with forming bases of said NPN transistors, adjacent another portion of said N - region to define an emitter-base junction of said PNP transistor; forming a second P + region substantially to the depth of said P - region, simultaneously with forming said first P + region, adjacent said P - region for establishing a collector contact region of said PNP transistor; and forming an N + region, simultaneously with forming collector reach-throughs of said PNP transistors, extending from the surface of said semiconducting region to said isolated N + region for establishing a base contact region of said PNP transistor.
Claim 2
Independent Claim
209 words
A method for making an asymmetrical lateral PNP transistor having a graded collector junction simultaneously with the process steps for making NPN transistors and P-type resistors, comprising the steps of: forming a semiconducting region into which said PNP and NPN transistors and said resistors are to be formed, by forming said semiconducting region containing isolated N + regions and overlying N - regions; forming at least one P - region, simultaneously with forming said resistors, one of said P - layers being adjacent a portion of one of said N - regions to define a collector-base junction of said PNP transistor; forming a first P + region, simultaneously with forming bases of said NPN transistors, adjacent another portion of said N - region to define an emitter-base junction of said PNP transistor; forming a second P + region substantially to the depth of said P - region, simultaneously with forming said first P + region, adjacent said P - region for establishing a collector contact region of said PNP transistor; and forming an N + region, simultaneously with forming collector reach-throughs of said PNP transistors, extending from the surface of said semiconducting region to said isolated N + region for establishing a base contact region of said PNP transistor.
Claim 3
Dependent Claim
78 words
A method for making an asymmetrical lateral PNP transistor, as recited in claim 1, wherein the step of forming the P - region comprises the steps of: forming a first mask layer over portions of said N - regions, said first mask layer defining a base width for said PNP transitor and an area for said P-type resistors; and introducing a P-type dopant into the areas of said N - regions not covered by said first mask layer.
Claim 4
Dependent Claim
26 words
A method for making an asymmetrical lateral PNP transistor, as recited in claim 2, wherein said introducing step is an ion-implantation into said N - region.
Claim 5
Dependent Claim
118 words
A method for making an asymmetrical lateral PNP transistor, as recited in claim 2, wherein the steps of forming said first and second P + regions comprise the steps of: removing said first mask layer in areas of said NPN transistors and said P-type resistors; then forming a second mask layer over portions of said first mask layer defining the PNP base width and over an adjacent portion of said P - region, said second mask layer further defining base contacts for said NPN transistors; and then introducing P-type dopants into said semiconductor region, said first and second mask layers blocking said introduction into overlaid areas, thereby forming an emitter and a collector contact of said PNP transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-15 | 1988-10-15 | 1989-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-15 | 1992-10-15 | 1993-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-15 | 1996-10-15 | 1997-04-16 | $7700.00 | Window Closed / Lapsed |