Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit having first and second transistors of opposite conductivity type, comprising: a. a semiconductor substrate of a first conductivity type; b. an epitaxial layer formation of a second conductivity type and relatively low impurity concentration formed on said substrate and having a major face opposite the substrate; c. said first transistor comprising: i. a first region of first conductivity type in said epitaxial layer formation spaced below said major face, and a conductive path region of first conductivity type and higher impurity concentration than said first region extending from the first region up to the major face; ii. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region; and iii. a third region of first conductivity type formed in said second region spaced from said first region by said second region; d. an isolating PN junction between said first transistor and said second transistor, said second transistor comprising: i. a fourth region of second conductivity type formed of a portion of said epitaxial layer formation isolated from the first transistor by the isolating PN junction; ii. a fifth region of first conductivity type spaced below said major face; and a conductive path region of first conductivity type and higher impurity concentration than said fifth region from the fifth region up to the major face; iii. a sixth region of second conductivity type being formed of said relatively low concentration epitaxial layer formation and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region; and iv. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward bias is applied between said fifth and sixth regions; whereby a first transistor is formed in an integrated circuit with a second transistor of low emitter concentration.

Claim 3

The integrated circuit of claim 1 in which a diffused portion of second conductivity type and concentration higher than said first transistor second region is formed in said second region to extend at least between said first region and third region, whereby said first transistor has a base of high impurity concentration and high breakdown voltage.

Claim 4

The integrated circuit of claim 1 in which the impurity concentration and gradient of said low-high junction is selected to have an electric field such that a drift current of minority carriers produced thereby substantially balances said diffusion current of minority carriers injected from the fifth region.

Claim 5

A semiconductor integrated circuit having first and second transistors of opposite conductivity type, comprising: a. a semiconductor substrate of a first conductivity type; b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite said substrate; c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate; d. a first transistor formed on one side of said isolation region comprising: i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and extending upwardly in said epitaxial layer formation, iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face and in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, v. a diffused region of second conductivity type and relatively higher concentration formed in said second region between said first region and major face, vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising: i. a third embedded region of second conductivity type formed in said substrate, ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded region, iii. a fifth region of first conductivity type in said fourth region spaced below said epitaxial layer formation major face and a conductive path region of first conductivity type and higher impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type being formed of said epitaxial layer formation of relatively low concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region, and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward-bias is applied between said fifth and sixth regions, whereby a first transistor of relatively high base concentration is formed with a second transistor of low emitter concentration.

Claim 6

A semiconductor integrated circuit having first and second transistors of opposite conductivity type, comprising: a. a semiconductor substrate of a first conductivity type; b. an epitaxial layer formation of a second conductivity type and relatively low concentration formed on said substrate and having a major face opposite said substrate; c. a first conductivity type isolation region in said epitaxial layer formation from said major face down to said substrate; d. a first transistor formed on one side of said isolation region comprising: i. a first embedded region of second conductivity type formed in said substrate, ii. a second embedded region of first conductivity type formed in said first embedded region and extending upwardly in said epitaxial layer formation, iii. a first region of first conductivity type formed in said epitaxial layer formation spaced below said major face and in contact with said second embedded region, and a conductive path region of first conductivity type and higher impurity concentration than said first region from the first region up to the major face, iv. a second region of second conductivity type being formed of said epitaxial layer formation and partially surrounded by said first region and conductive path region, v. a diffused region of second conductivity type and relatively higher concentration formed in said second region between said first region and major face, vi. a third region of first conductivity type formed in said diffusion region and spaced from said first region by said diffusion region, e. a second transistor formed on the other side of said isolation region comprising: i. a third embedded region of second conductivity type formed in said substrate, ii. a fourth region of second conductivity type and lower concentration than said third embedded region formed by said epitaxial layer formation in contact with said third embedded region, iii. a fifth region of first conductivity type in said fourth region spaced below said epitaxial layer formation major face and a conductive path region of first conductivity type and higher impurity concentration than said fifth region from the fifth region up to the major face, iv. a sixth region of second conductivity type being formed of said epitaxial layer formation of relatively low concentration and partially surrounded by said fifth region and conductive path region, said sixth region being spaced from said fourth region by said fifth region, and v. a seventh region of second conductivity type and concentration relatively higher than said sixth region formed in said sixth region and forming a low-high concentration barrier junction therewith, said junction being spaced from said fifth region by a distance less than the diffusion length of minority carriers in said sixth region injected from said fifth region when a forward-bias is applied between said fifth and sixth regions, whereby a first transistor of relatively high base concentration is formed with a second transistor of low emitter concentration.

Claim 7

The integrated circuit of claim 4 in which the first transistor first region first portion has an impurity concentration relatively lower than impurity concentration of said second embedded region whereby a low concentration collector region is formed adjacent a base in said first transistor.