Abstract In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p - -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p - -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p - -regions (40) and (49) are formed simultaneously with the p - -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p - -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h FE transistor, high speed vertical npn transistor, cross-over devices, p-channel and/or n-channel MOS transistors can be formed within limited manufacturing steps.
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; forming a sixth region of an n-type in said fourth region from a upper surface of said fourth region; simultaneously forming seventh, eight and ninth regions of p-type in said sixth, fifth and third regions respectively from upper surfaces of said sixth, fifth and third regions; and simultaneously forming tenth and eleventh regions of n-type in said sixth and ninth regions from upper surfaces of said sixth and ninth regions, respectively, whereby said fourth, sixth and seventh regions form a pnp type vertical bipolar transistor, and said fifth and eight regions from a resistance device, and said third, ninth and eleventh regions forming an npn type vertical bipolar transistor.
Claim 2
Independent Claim
170 words
A method of fabricating a semiconductor integrated circuit, comprising the steps of: forming a n-type semiconductor layer on a p-type semiconductor substrate, said n-type semiconductor layer being divided into first, second and third regions of n-type; simultaneously forming fourth and fifth regions of low p-type concentration in said first and second regions as upper surfaces of said first and second regions; forming a sixth region of an n-type in said fourth region from a upper surface of said fourth region; simultaneously forming seventh, eight and ninth regions of p-type in said sixth, fifth and third regions respectively from upper surfaces of said sixth, fifth and third regions; and simultaneously forming tenth and eleventh regions of n-type in said sixth and ninth regions from upper surfaces of said sixth and ninth regions, respectively, whereby said fourth, sixth and seventh regions form a pnp type vertical bipolar transistor, and said fifth and eight regions from a resistance device, and said third, ninth and eleventh regions forming an npn type vertical bipolar transistor.
Claim 3
Dependent Claim
60 words
A method as in claim 1, comprising the further steps of: forming a twelfth region of n-type at a border area of said first region and said semiconductor substrate; and forming a thirteenth region of n-type in said first region from said upper surface of said first region in such a manner that said thirteenth region reaches said twelfth region.
Claim 4
Dependent Claim
20 words
A method as in claim 2, comprising the further step of electrically connecting said sixth region to said thirteenth region.